ispPAC-POWR6AT6-01SN32I Lattice, ispPAC-POWR6AT6-01SN32I Datasheet - Page 25

• Manufacturer Part Number: ispPAC-POWR6AT6-01SN32I
• Description: Supervisory Circuits Prec Prog Pwr Supply Seq Mon Trim IND
• Manufacturer: Lattice
• Series: ispPAC®r

Specifications of ispPAC-POWR6AT6-01SN32I

• Number Of Voltages Monitored: 6
• Monitored Voltage: Adjustable
• Undervoltage Threshold: Adjustable
• Overvoltage Threshold: Adjustable
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Supply Voltage (max): 3.96 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 10000 uA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFNS-32
• Minimum Operating Temperature: - 40 C
• Applications: Power Supply Controller/Monitor
• Voltage - Input: -0.3 V ~ 5.9 V
• Voltage - Supply: 2.8 V ~ 3.96 V
• Current - Supply: 10mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 3-22. SMBAlert Bus Transaction
After CLTLOCK/SMBA has been released, the bus master (typically a microcontroller) may opt to perform some
service functions in which it may send data to or read data from the ispPAC-POWR6AT6. As part of the service
functions, the bus master will typically need to clear whatever condition initiated the SMBAlert request (power sup-
ply malfunction, etc.). For further information on the SMBus functionality, the user should consult the SMBus Stan-
dard.
Software-Based Design Environment
Designers can configure the ispPAC-POWR6AT6 using PAC-Designer, an easy to use, Microsoft Windows compat-
ible program. Circuit designs are entered graphically and then verified, all within the PAC-Designer environment.
Full device programming is supported using PC parallel port I/O operations and a download cable connected to the
serial programming interface pins of the ispPAC-POWR6AT6. A library of configurations is included with basic solu-
tions and examples of advanced circuit techniques are available on the Lattice web site for downloading. In addi-
tion, comprehensive on-line and printed documentation is provided that covers all aspects of PAC-Designer
operation. The PAC-Designer schematic window, shown in Figure 3-23, provides access to all configurable ispPAC-
POWR6AT6 elements via its graphical user interface. All analog input and output pins are represented. Static or
non-configurable pins such as power, ground, and the serial digital interface are omitted for clarity. Any element in
the schematic window can be accessed via mouse operations as well as menu commands. When completed, con-
figurations can be saved, simulated, and downloaded to devices.
Figure 3-23. PAC-Designer ispPAC-POWR6AT6 Design Entry Screen
SMBA
6. If transmitted device address matches ispPAC-POWR6AT6 address, the master completes the cycle by set-
SDA
SCL
ting the I
high).
ASSERTS
SLAVE
SMBA
2
C closed loop trim register SMBA bit low again. This releases the CLTLOCK/SMBA pin (it goes
START
0
1
0
2
ALERT RESPONSE ADDRESS
0
3
1
4
(0001 100)
1
5
0
6
7
0
R/W
8
3-25
ACK
9
A6
1
A5
2
A4
SLAVE ADDRESS (7 BITS)
3
ispPAC-POWR6AT6 Data Sheet
A3
4
A2
5
A1
6
A0
7
Note: Shaded Bits Asserted by Slave
8
x
ACK
9
RELEASES
SLAVE
SMBA
STOP