ST7538Q STMicroelectronics, ST7538Q Datasheet - Page 23

• Manufacturer Part Number: ST7538Q
• Description: IC TXRX FSK POWER LINE 44-TQFP
• Manufacturer: STMicroelectronics
• Type: Transceiverr

Specifications of ST7538Q

• Number Of Drivers/receivers: 1/1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 44-TQFP Exposed Pad, 44-eTQFP, 44-HTQFP, 44-VQFP
• For Use With: 497-5484 - BOARD EVAL ST7538 PWR LINE TXRX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Protocol: -
• Other names: 497-5525

ST7538Q
5.7
5.7.1
5.7.2
Receiving mode
The receive section is active when RxTx Pin = ”1” and REG_DATA = 0.
The input signal is read on RAI Pin using SGND as ground reference and then pre-filtered
by a Band pass Filter (62kHz max bandwidth at -3dB). The Pre-Filter can be inserted setting
one bit in the Control Register. The Input Stage features a wide dynamic range to receive
Signal with a Very Low Signal to Noise Ratio. The Amplitude of the applied waveform is
automatically adapted by an Automatic Gain Control block (AGC) and then filtered by a
Narrow Band Band-Pass Filter centered around the Selected Channel Frequency (14kHz
max at -3dB). The resulting signal is down-converted by a mixer using a sinewave generated
by the FSK Modulator. Finally an Intermediate Frequency Band Pass-Filter (IF Filter)
improves the Signal to Noise ration before sending the signal to the FSK demodulator. The
FSK demodulator then send the signal to the RX Logic for final digital filtering. Digital
filtering Removes Noise spikes far from the BAUD rate frequency and Reduces the Signal
Jitter. RxD Line is forced at logic level “0” or “1” (according the UART/SPI pin level) when
neither mark or space frequencies are detected on RAI Pin.
Mark and Space Frequency in Receiving Mode must be distant at least BaudRate/2 to have
a correct demodulation.
While ST7538Q is in Receiving Mode (RxTx pin = ”1”), the transmit circuitry, Power Line
Interface included, is turned off. This allows the device to achieve a very low current
consumption (5mA typ). In Receiving mode ATOP2 pin is internally connected to PAVSS.
High sensitivity mode
It is possible to increase the ST7538Q Receiving Sensitivity setting to ‘1’ the High Sensitivity
Bit of Control Register
when the ST7538Q sensitivity is the limiting factor.
Synchronization recovery system (PLL)
ST7538Q embeds a Clock Recovery System to feature a Synchronous data exchange with
the Host Controller.
The clock recovery system is realized by means of a second order PLL. Data on the data
line (RxD) are stable on CLR/T line rising edge (CLR/T Falling edge synchronized to RxD
line transitions ± LOCK-IN Range).
The PLL Lock-in and Lock-out Range is ±π/2. When the PLL is in the unlock condition,
CLR/T and RxD lines are forced to a low logic level.
When PLL is in unlock condition it is sensitive to RxD Rising and Falling Edges. The
maximum number of transition required to reach the lock-in condition is 5. When in lock-in
condition the PLL is sensitive only to RxD rising Edges to reduce the CLR/T Jitter.
ST7538Q PLL is forced in the un-lock condition, when more than 32 equal symbols are
received.
Due to the fact that the PLL, in lock-in condition, is sensitive only to RxD rising edge,
sequences equal or longer than 15 equal symbols can put the PLL into the un-lock
condition.
b. A third level of Rx sensitivity can be selected in UART Interface Mode (see par. 5.11)
(b)
. This function allows to increase the communication reliability
Functional description
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