ST7538Q STMicroelectronics, ST7538Q Datasheet - Page 18

• Manufacturer Part Number: ST7538Q
• Description: IC TXRX FSK POWER LINE 44-TQFP
• Manufacturer: STMicroelectronics
• Type: Transceiverr

Specifications of ST7538Q

• Number Of Drivers/receivers: 1/1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 44-TQFP Exposed Pad, 44-eTQFP, 44-HTQFP, 44-VQFP
• For Use With: 497-5484 - BOARD EVAL ST7538 PWR LINE TXRX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Protocol: -
• Other names: 497-5525

Functional description
5.5
18/44
In Data Reception Mode:
Host processor interface
ST7538Q exchanges data with the host processor through a serial interface.
The data transfer is managed by REG_DATA and RxTx Lines, while data are exchanged
using RxD, TxD and CLR/T lines.
Four are the ST7538Q working modes:
●
●
●
●
REG_DATA and RxTx lines are level sensitive inputs.
Table 8. Data and control register access bits configuration
ST7538Q features two type of Host Communication Interfaces:
The selection can be done through the UART/SPI pin. If UART/SPI pin is forced to “0” SPI
interface is selected while if UART/SPI pin is forced to “1” UART interface is selected
type of interface affects the Data Reception by setting the idle state of RxD line. When
ST7538Q is in Receiving mode (REG_DATA=”0” and RxTx =“1”) and no data are available
on mains (or RxD is forced to an idle state, i.e. with a conditioned Detection Method), the
RxD line is forced to “0” when UART/SPI pin is forced to ”0” or to “1” when UART/SPI pin is
forced to ”1”.
a. UART Interface Mode modifies also Control Register Functions and provides one more level of Rx sensitivity
Data Transmission
Data Reception
Control Register Read
Control Register Write
(see par. 5.11)
–
–
Data Reception
Data Transmission
Control Register Read
Control Register Write
–
–
Synchronous Mains access: on clock signal recovered by a PLL from ST7538Q
(CLR/T line) rising edge, value on FSK Demodulator is read and put to the data
reception line (RxD line). ST7538Q recovers the bit timing according to the
BaudRate Selected.
Asynchronous Mains access: Value on FSK Demodulator is sent directly to the
data reception line (RxD line). The Host Controller recovers the communication
timing (CLR/T line should be neglected).
SPI
UART
REG_DATA
0
0
1
1
RxTx
1
1
0
0
ST7538Q
(a)
. The