ST7538Q STMicroelectronics, ST7538Q Datasheet
ST7538Q
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ST7538Q Summary of contents
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... ST7538QTR July 2006 FSK power line transceiver TQFP44 Slug Down Description The ST7538Q is a Half Duplex synchronous/asynchronous FSK Modem designed for power line communication network applications. It operates from a single supply voltage and integrates a line driver and two linear regulators for 5V and 3.3V. The device operation ...
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... Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 Carrier frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 Baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 Mark and space frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4 ST7538Q mains access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.5 Host processor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.5.1 5.6 Control register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.7 Receiving mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.7.1 5.7.2 5.7.3 5.7.4 5.8 Transmission mode ...
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... ST7538Q 6 Auxiliary analog and digital functions . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1 Band in use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.2 Time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.3 Reset & watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.4 Zero crossing detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.5 Output clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.6 Output voltage level freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.7 Extended control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.8 Reg 6.9 Under voltage lock out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.10 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6 ...
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... TEST DIGITAL FSK IF FILTER DEMOD FILTER CONTROL REGISTER FSK TX DAC MODULATOR FILTER ZC OP-AMP + - RSTO MCLK ZCout ZCin C_OUT CMINUS CPLUS ST7538Q BU RxFo BU AGC FILTER AMPL FILTER CURRENT CONTROL VOLTAGE ALC CONTROL PLI VREG D03IN1407A DVdd DVss RAI CL Vsense ATO ATOP1 ATOP2 ...
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... ST7538Q 2 Pin settings 2.1 Pin connection Figure 2. Pin Connection (Top view CD_PD 1 DVSS 2 RXD 3 RxTx 4 TXD 5 GND 6 TOUT 7 CLR DVDD 10 MCLK Pin settings VDC 33 RAI 32 RXFO 31 TEST2 30 VSENSE 29 AVDD 28 XIN 27 XOUT 26 SGND 25 ATO D01IN1312 5/44 ...
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... Power Line Driver Output Power Analog Ground Power Line Driver Output Power Supply Voltage Current Limiting Feedback. A resistor between CL and AVss sets the PLI Current Limiting Value An integrated 80pF filtering input capacitance is present on this pin Small Signal Analog Transmit Output ST7538Q ...
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... ST7538Q Table 1. Pin description (continued) Pin N° Name Type 25 SGND Supply 26 XOUT Analog Output 27 XIN Analog Input 28 AVdd Supply 29 (3) Analog/Input Vsense 30 TEST2 Analog/Input 31 RxFO Analog/Output 32 RAI Analog/Input 33 VDC Power 34 NC floating 35 TEST1 Digital/Input with internal pull-down 36 REGOK Digital/Output 37 (4) Analog/Input ...
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... Maximum Withstanding Voltage Range Pin Test Condition: CDF-AEC-Q100-002- “Human Body Model” Other Acceptance Criteria: “Normal Performance” pins 1. This current is intended as not repetitive pulse current 8/44 Parameter and (1) ST7538Q Value Unit -0.3 to +14 V -0.3 to +5.5 V -0.3 to +5.5 V -0 +0.3 ...
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... ST7538Q 3.2 Thermal data Table 3. Thermal data Symbol Maximum Thermal Resistance Junction-Ambient R thJA1 Steady state Maximum Thermal Resistance Junction-Ambient R thJA2 Steady state 1. Mounted on Multilayer PCB with a dissipating surface on the bottom side of the PCB 2. It's the same condition of the point above, without any heatsinking surface on the board. ...
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... Min -2mA DVdd -0. 2mA OL 1 -2mA DVdd -0. 2mA OL External Clock. Figure 19 External Clock. Figure 19 External Clock. Figure 19 40 Fundamental R = 1.75kΩ CL 1.75 Vsense = 0V (AC) 1.7 ST7538Q < 125 ° 86kHz, J Typ Max Unit V 1 DVss + 0 0 DVss + 0 2 MHz 62.5 ns Ω mArms V 2 ...
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... ST7538Q Table 4. Electrical characteristics (continued) (AVdd = DVdd = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V, -40°C ≤ T other control register parameters as default value, unless otherwise specified) Symbol Parameter Second Harmonic HD2 ATO Distortion on ATO Third Harmonic Distortion HD3 ATO on ATO Output Transmitting IATOP ...
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... Figure 17- 1200 Baud Xtal=16MHz Figure 17- 2400 Baud Xtal=16MHz Figure 17- 4800 Baud Xtal=16MHz Figure 17 Xtal =16MHz Figure 17 Xtal =16MHz UART/SPI pin forced to “1” ST7538Q ≤ 85°C, T < 125 ° 86kHz, J Min Typ Max 80 1.80 1.90 2.00 210 250 290 0.01 1.6 ...
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... ST7538Q Table 4. Electrical characteristics (continued) (AVdd = DVdd = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V, -40°C ≤ T other control register parameters as default value, unless otherwise specified) Symbol Parameter 5V voltage regulator Linear regulator output VDC voltage Power Good Output PG Voltage Threshold on VDC VDC pin ...
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... Table 11 Figure 22 -45 5 -20 15 -30 -38 6 see Figure & 9 see Figure & 9 see Figure & see Figure & see Figure & see Figure & ST7538Q < 125 ° 86kHz, J Typ Max Unit 1667 833 µs 417 208 µ + -20 - MHz 2 ...
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... Table 5. ST7538Q Channels List 5.2 Baud rates ST7538Q is a multi Baud rate device: four Baud Rate are available (See Table 6. ST7538Q mark and space tones frequency distance vs baud rate and deviation Baud Rate [Baud] 600 1200 (4) 2400 4800 1 ...
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... With Deviation = “0.5” the difference in terms of frequency between the mark and space tones is half the Baudrate value (∆F = 0.5*BAudrate). When the Deviation = “1” the difference is the Baudrate itself (∆F = Baudrate). The minimal Frequency Deviation is 600Hz. Table 7. ST7538Q synthesized frequencies Carrier Baud Frequency ...
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... Reception Mode (for how to set the communication Mode, see In Data Transmission Mode: – Synchronous Mains access: on clock signal provided by ST7538Q (CLR/T line) rising edge, data transmission line (TxD line) value is read and sent to the FSK Modulator. ST7538Q manages the Transmission timing according to the BaudRate Selected. – ...
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... UART/SPI pin is forced to “1” UART interface is selected type of interface affects the Data Reception by setting the idle state of RxD line. When ST7538Q is in Receiving mode (REG_DATA=”0” and RxTx =“1”) and no data are available on mains (or RxD is forced to an idle state, i.e. with a conditioned Detection Method), the RxD line is forced to “ ...
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... Synchronous and asynchronous ST7538Q/Host controller interfaces Host Controller ST7538Q allows to interface the Host Controller using a five line interface (RxD,TxD,RxTx, CLR/T, & REG_DATA) in case of Synchronous mains access or using a 3 line interface (RxD,TxD & RxTx) in Asynchronous mains access. Since Control Register is not accessible in Asynchronous mode, in this case REG_DATA pin can be tied to GND ...
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... Mode and control the Bit time in transmission mode. If RxTx line is set to “1” & REG_DATA = ”0” (Data Reception), ST7538Q enters in an Idle State. After Tcc time the modem starts providing received data on RxD line. ...
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... The Data on RxD are stable on CLR/T rising edges MSB First. In Normal Control Register mode 24 bits are transferred from ST7538Q to the Host. In Extended Control Register mode bits are transferred from ST7538Q to the Host depending on content of Control Register bit 18 (with bit 18 = ”0” the first 24 bits are transferred, otherwise all 48 bits are ...
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... Data transmission -> control reg. read data -> reception timing diagram CLR_T T B RxD REG_DATA RxTx TxD Figure 9. Data transmission -> control reg. write -> data reception timing diagram CLR_T T B TxD REG_DATA RxTx RxD 22/ BIT23 BIT22 BIT23 BIT22 BIT23 BIT22 BIT23 BIT22 T CR ST7538Q D03IN1404 D03IN1403 D03IN1405 D03IN1401 ...
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... When in lock-in condition the PLL is sensitive only to RxD rising Edges to reduce the CLR/T Jitter. ST7538Q PLL is forced in the un-lock condition, when more than 32 equal symbols are received. Due to the fact that the PLL, in lock-in condition, is sensitive only to RxD rising edge, sequences equal or longer than 15 equal symbols can put the PLL into the un-lock condition ...
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... Functional description Figure 10. ST7538Q PLL lock-in range CLR/T RxD 5.7.3 Carrier/preamble detection The Carrier/Preamble Block is a digital Frequency detector Circuit. It can be used to manage the MAINS access and to detect an incoming signal. Two are the possible setting: ● Carrier detection: The Carrier/Preamble detection Block notifies to the host controller the presence of a Carrier when it detects on the RAI Input a signal with an harmonic component close to the programmed Carrier Frequency ...
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... ST7538Q Figure 11. CD_PD timing during RX CD_PD RAI RxD (UART/SPI="1") RxD (UART/SPI="0") Figure 12. Receiving path block diagram 3 RxD Bits 3-4 &14 8 CLR/T PLL Bits 18-21 & 24-47 HEADER 1 CD_PD RECOGN DCD CD demodulation active on RxD pin Bits 3-4 Bits 3-4 & 22 ...
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... FSK modulator. ● Host Controller Synchronous Communication Mode: on CLR/T rising edge, TXD Line Value is read and sent to the FSK Modulator. ST7538Q Manages the Transmission timing according to the BaudRate Selected ● Host Controller Asynchronous Communication Mode: TXD data enter directly to the FSK Modulator ...
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... ST7538Q 5.8.1 Automatic Level Control (ALC) The Automatic Level Control Block (ALC variable gain amplifier (with 32 non linear discrete steps) controlled by two analog feed backs acting at the same time. The ALC gain range is 0dB and the gain change is clocked at 5KHz. Each step increases or reduces the voltage of 1dB (Typ) ...
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... Irms (mA) 325 300 275 250 225 200 175 150 125 100 2 2.5 3 3.5 4 ST7538Q ± ) VCL HYST R2 (KΩ) R1 (KΩ) 7.5 1.0 5.1 3.9 3.6 5.6 3.3 8.2 3.3 11.0 2.7 12.0 2.0 11.0 1.6 10 ...
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... ST7538Q ● Integrated Power Line Interface (PLI) The Power Line Interface (PLI double CMOS AB Class Power Amplifier with the two outputs (ATOP1 and ATOP2) in opposition of phase. Two are the possible configuration: - Single Ended Output (ATOP1). - Bridge Connection The Bridge connection guarantee a Differential Output Voltage to the load with twice the swing of each individual Output ...
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... ATOP2 5.9 Crystal oscillator ST7538Q integrates a inverter driver circuit to realize a 16MHz crystal oscillator. This circuit is able to drive a maximum load capacitance of 16pF with typical quartz ESR of 40Ω the internal driver circuit is used, only one external crystal quartz and two external load ...
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... ST7538Q Figure 19. XIN waveform if an external oscillator is used 5.10 Control register The ST7538Q is a multi-channel and multifunction transceiver. An internal Bits (in Extended mode) Control Register allows to manage all the programmable parameters (Table 11). The programmable functions are: ● Channel Frequency ● Baud Rate ● ...
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... KHz Bit 4 Bit 3 600 0 0 1,200 0 1 2,400 1 0 4,800 1 1 Bit 5 0 Bit 6 Disabled 0 Enabled (1 Bit 8 Bit 7 Disabled Not Used 1 1 Bit 10 Bit 9 500 µ Bit 11 Disabled 0 Enabled 1 ST7538Q Note Default 132.5 kHz 2400 0.5 Enabled 1 sec 1 ms Disabled ...
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... ST7538Q Table 11. Control register functions (continued) Function Detection Method Mains 14 Interfacing Mode 15 to Output Clock 16 Output 17 Voltage Level Freeze Header 18 Recognition Frame 19 Length Count Value Selection Bit 13 Carrier detection without 0 conditioning Carrier detection 0 with conditioning Preamble detection 1 (1) without conditioning Preamble ...
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... Bit 22 Normal 0 Sensitivity 1 High Sensitivity Bit 23 Disabled 0 Enabled 1 from 0000h to FFFFh from 01h to FFh ST7538Q Note Default Active only if Extended Control Register is 16 bits enable (Bit 21=”1”) Extended Register Disabled enables Functions on (24 bits) Bit 17, 18,19 and 20 Normal Disabled One 16 bits Header or ...
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... ST7538Q 5.11 Detection method and Rx Sensitivity in UART mode When ST7538Q is running in UART mode (by forcing UART/SPI pin to “1”) the Control Register Function “Detection method” differs from SPI mode as indicated in the Table 12. Control register functions in UART mode Function 12 to Detection 13 Method ...
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... RSTO Output is a reset generator for the application circuitry. During the ST7538Q startup sequence is forced low. RSTO becomes high after a T startup sequence. Inside ST7538Q is also embedded a watchdog function. The watchdog function is used to detect the occurrence of a software fault of the Host Controller. The watchdog circuitry generates an internal and external reset (RSTO low for T watchdog timer ...
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... ST7538Q Figure 21. Reset and watchdog timing T RSTO RSTO WD 6.4 Zero crossing detection The Mains Voltage Zero Crossing can be detected, through a proper connection of ZCIN to the Mains. ZCIN comparator has a threshold fixed at SGND. ZCOUT is a TTL Output forced High after a positive zero-crossing transition, and low after a negative one. ...
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... Thermal shutdown The ST7538Q is provided of a thermal protection which turn off the PLI when the junction temperature exceeds 170°C ± 10% . Hysteresis is around 30°C. When shutdown threshold is overcome, PLI interface is switched OFF. Thermal Shutdown event is notified to the HOST controller using TIMEOUT line. When TIMEOUT line is High, ST7538Q junction temperature exceed the shutdown threshold (Not Leached) ...
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... ST7538Q 6.11 5V and 3.3V voltage regulators and power good function ST7538Q has an embedded 5V linear regulator externally available to supply the application circuitry. The linear regulator has a very low quiescent current (50µA) and a current capability of 50mA. The regulator is protected against short circuitry events. ...
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... Auxiliary analog and digital functions 6.12 Power-up procedure To ensure ST7538Q proper power-Up sequence, PAVcc, AVdd and DVdd Supply has to fulfil the following rules: PAVcc rising slope must not exceed 100V/ms. When DVdd is below 5V/3.3V and AVdd is below 5V: 100mV < PAVcc-AVdd , PAVcc-DVdd < ...
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... ST7538Q Figure 25. Application schematic example with coupling tranformer. Auxiliary analog and digital functions 41/44 ...
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... Copper slug to the ground layer on the soldering side. Moreover it is recommitted to connect the ground layer on the soldering side to another ground layer on the opposite side with vias suggested to not use the PCB surface below the slug area to interconnect any pin except ground pins. Figure 26. ST7538Q slug drawing Figure 27. Soldering information Cu plate A 42/44 www ...
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... ST7538Q 8 Revision history Table 13. Revision history Date 12-Jul-2006 Revision 1 Initial release. Revision history Changes 43/44 ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 44/44 Please Read Carefully: © 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com ST7538Q ...