ICS1893YI-10LF IDT, Integrated Device Technology Inc, ICS1893YI-10LF Datasheet - Page 98

• Manufacturer Part Number: ICS1893YI-10LF
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893YI-10LF

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 1893YI-10LF

7.13.2 Polarity Reversed (bit 18.14)
7.13.3 ICS Reserved (bits 18.13:6)
7.13.4 Jabber Inhibit (bit 18.5)
7.13.5 ICS Reserved (bit 18.4)
7.13.6 Auto Polarity Inhibit (bit 18.3)
7.13.7 SQE Test Inhibit (bit 18.2)
ICS1893Y-10 Rev F 1/20/04
The Polarity Reversed bit is used to inform an STA whether the ICS1893Y-10 has detected that the signals
on the Twisted-Pair Receive Pins (TP_RXP and TP_RXN) are reversed. When the signal polarity is:
•
•
Note:
See
The Jabber Inhibit bit allows an STA to disable Jabber Detection. When an STA sets this bit to:
•
•
See
The Auto Polarity Inhibit bit allows an STA to prevent the automatic correction of a polarity reversal on the
Twisted-Pair Receive pins (TP_RXP and TP_RXN). If an STA sets this bit to logic:
•
•
Note:
The SQE Test Inhibit bit allows an STA to prevent the generation of the Signal Quality Error pulse. When an
STA sets this bit to logic:
•
•
The SQE Test provides the ability to verify that the Collision Logic is active and functional. A 10Base-T SQE
test is performed by pulsing the Collision signal for a short time after each packet transmission completes,
that is, after TXEN goes inactive.
Note:
1. The SQE Test is automatically inhibited in full-duplex and repeater modes, thereby disabling the
2. This bit is a control bit and not a status bit. Therefore, it is not updated to indicate this automatic
Correct, the ICS1893Y-10 sets bit 18.14 to a logic zero.
Reversed, the ICS1893Y-10 sets bit 18.14 to logic one.
Zero, the ICS1893Y-10 enables 10Base-T Jabber checking.
One, the ICS1893Y-10 disables its check for a Jabber condition during data transmission.
Zero (the default), the ICS1893Y-10 automatically corrects a polarity reversal on the Twisted-Pair
Receive pins.
One, the ICS1893Y-10 either disables or inhibits the automatic correction of reversed Twisted-Pair
Receive pins.
Zero, the ICS1893Y-10 enables its SQE Test generation.
One, the ICS1893Y-10 disables its SQE Test generation.
functionality of this bit.
inhibiting of the SQE test in full-duplex mode or repeater mode.
Section 7.11.2, “ICS Reserved (bits
Section 7.11.2, “ICS Reserved (bits
ICS1893Y-10 Data Sheet - Release
The ICS1893Y-10 can detect this situation and perform all its operations normally, independent of
the reversal.
This bit is also used to correct a reversed signal polarity for 100Base-TX operations.
Copyright © 2004, Integrated Circuit Systems, Inc.
16.14:11)”, the text for which also applies here.
16.14:11)”, the text for which also applies here.
All rights reserved.
98
Chapter 7 Management Register Set
January, 2004