ICS1893YI-10LF IDT, Integrated Device Technology Inc, ICS1893YI-10LF Datasheet - Page 90

• Manufacturer Part Number: ICS1893YI-10LF
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893YI-10LF

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 1893YI-10LF

7.11.1 Command Override Write Enable (bit 16.15)
7.11.2 ICS Reserved (bits 16.14:11)
7.11.3 PHY Address (bits 16.10:6)
7.11.4 Stream Cipher Scrambler Test Mode (bit 16.5)
7.11.5 ICS Reserved (bit 16.4)
7.11.6 NRZ/NRZI Encoding (bit 16.3)
ICS1893Y-10 Rev F 1/20/04
The Command Override Write Enable bit provides an STA the ability to alter the Command Override Write
(CW) bits located throughout the MII Register set. A two-step process is required to alter the value of a CW
bit:
1. Step one is to issue a Command Override Write, (that is, set bit 16.15 to logic one). This step enables
2. Step two is to write to the register that includes the CW bit which requires modification.
Note:
ICS is reserving these bits for future use. Functionally, these bits are equivalent to IEEE Reserved bits.
When one of these reserved bits is:
•
•
ICS uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the ICS1893Y-10,
an STA must maintain the default value of these bits. Therefore, ICS recommends that an STA always write
the default value of any reserved bits during all management register write operations.
These five bits hold the Serial Management Port Address of the ICS1893Y-10. During either a hardware
reset or a power-on reset, the PHY address is read from the LED interface. (For information on the LED
interface, see
Address and LED
Address bits is unaffected by a software reset.)
The Stream Cipher Scrambler Test Mode bit is used to force the ICS1893Y-10 to lose LOCK, thereby
requiring the Stream Cipher Scrambler to resynchronize.
See
This bit allows an STA to control whether NRZ (Not Return to Zero) or NRZI (Not Return to Zero, Invert on
One) encoding is applied to the serial transmit data stream in 100Base-TX mode. When this bit is logic:
•
•
Read by an STA, the ICS1893Y-10 returns a logic zero.
Written to by an STA, the STA must use the default value specified in this data sheet.
Zero, the ICS1893Y-10 encodes the serial transmit data stream using NRZ encoding.
One, the ICS1893Y-10 encodes the serial transmit data stream using NRZI encoding.
the next MDIO write to have the ability to alter any CW bit.
Section 7.11.2, “ICS Reserved (bits
ICS1893Y-10 Data Sheet - Release
The Command Override Write Enable bit is a Self-Clearing bit that is automatically reset to logic
zero after the next MII write, thereby allowing only one subsequent write to alter the CW bits in a
single register. To alter additional CW bits, the Command Override Write Enable bit must once
again be set to logic one.
Section 5.8, “Status Interface”
Pins”). The PHY address is then latched into this register. (The value of each of the PHY
Copyright © 2004, Integrated Circuit Systems, Inc.
16.14:11)”, the text for which also applies here.
All rights reserved.
and
90
Section 8.3.2, “Multi-Function (Multiplexed) Pins: PHY
Chapter 7 Management Register Set
January, 2004