ICS1893CY-10LF IDT, Integrated Device Technology Inc, ICS1893CY-10LF Datasheet - Page 74

• Manufacturer Part Number: ICS1893CY-10LF
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893CY-10LF

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 1893CY-10LF; 800-1025

7.6.5 Technology Ability Field (bits 4.9:5)
7.6.5.1 Technology Ability Field: Hardware Mode
ICS1893CY-10 Rev 1/07
When its Auto-Negotiation sublayer is enabled, the ICS1893CY-10 transmits its link capabilities to its
remote link partner during the auto-negotiation process. The Technology Ability Field (TAF) bits 4.12:5
determine the specific abilities that the ICS1893CY-10 advertises. The ISO/IEC specification defines the
TAF technologies in Annex 28B.
The ISO/IEC specification reserves bits 4.12:10 for future use. When each of these reserved bits is:
•
•
ICS uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the
ICS1893CY-10, an STA must maintain the default value of these bits. Therefore, ICS recommends that an
STA always write the default value of any reserved bits during all management register write operations.
Reserved bits 4.12:10 are Command Override Write (CW) bits. Whenever bit 16.15 (the Command
Register Override bit) is logic:
•
•
Each of the bits 4.9:5 in the TAF represent a specific technology capability. When one of these bits is logic:
•
•
With the exception of bit 4.9, the default settings of the TAF bits depend on the ICS1893CY-10 operating
mode. Bit 4.9 is always logic zero, indicating that the ICS1893CY-10 cannot support 100Base-T4
operations.
When the ICS1893CY-10 is operating in hardware mode (that is, the HW/SW pin is logic zero), these TAF
bits are Read-Only bits. The default value of these bits depends on the signal level on the HW/SW pin and
whether the Auto-Negotiation sublayer is enabled.
In hardware mode, with the ANSEL pin pulled:
•
•
Read by an STA, the ICS1893CY-10 returns a logic zero
Written to by an STA, the STA must use the default value specified in this data sheet
Zero, the ICS1893CY-10 isolates all STA writes to CW bits, including bits 4.12:10.
One, an STA can modify the value of bits 4.12:10
Zero, it indicates to the remote link partner that the local device cannot support the technology
represented by the bit.
One, it indicates to the remote link partner that the local device can support the technology.
Low to a disabled state, the ICS1893CY-10 does not execute the auto-negotiation process. Upon
completion of the initialization sequence, the ICS1893CY-10 proceeds to the idle state and begins
‘sending idles’ according to the technology mode selected by the 10/100SEL pin and the DPXSEL pin. In
this mode, the values of the TAF bits (bits 4.8:5) are undefined.
High to an enabled state, the ICS1893CY-10 executes the auto-negotiation process and advertises its
capabilities to the remote link partner immediately following reset. The 10/100SEL and DPXSEL input
pins determine the single capability that the ICS1893CY-10 advertises. The ICS1893CY-10 updates the
Auto-Negotiation Advertisement Register TAF field to indicate the selection made by these pins. The
ICS1893CY-10 sets only one of these four bits to logic one. The other three bits are a logic zero.
Note:
ICS1893CY-10 Data Sheet - Release
The ICS1893CY-10 does not alter the value of the Status Register bits. Although the
ICS1893CY-10 is advertising only one technology, the ISO/IEC definitions for the Status
Register bits require these bits to indicate all the capabilities of the ICS1893CY-10.
Copyright © 2007, Integrated Device Technology Inc.
All rights reserved.
74
Chapter 7 Management Register Set