PIC18F46K80-I/ML Microchip Technology Inc., PIC18F46K80-I/ML Datasheet - Page 288

• Manufacturer Part Number: PIC18F46K80-I/ML
• Description: 44 QFN 8X8X0.9MM TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F46K80-I/ML

• A/d Inputs: 11-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 35
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin QFN
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F66K80 FAMILY
REGISTER 20-4:
20.4.7
In Single Output mode, pulse steering allows any of the
PWM pins to be the modulated signal. Additionally, the
same PWM signal can simultaneously be available on
multiple pins.
Once
(CCP1M<3:2> = 11 and P1M<1:0> = 00 of the
CCP1CON register), the user firmware can bring out
the same PWM signal to one, two, three or four output
pins by setting the appropriate STR<D:A> bits
(PSTR1CON<3:0>), as provided in
DS39977C-page 288
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-0
Note:
P1RSEN
R/W-0
the
PULSE STEERING MODE
The associated TRIS bits must be set to
output (‘ 0 ’) to enable the pin output driver
in order to see the PWM signal on the pin.
Single
P1RSEN: PWM Restart Enable bit
1 = Upon auto-shutdown, the ECCP1ASE bit clears automatically once the shutdown event goes
0 = Upon auto-shutdown, ECCP1ASE must be cleared by software to restart the PWM
P1DC<6:0>: PWM Delay Count bits
P1DCn = Number of F
P1DC6
R/W-0
away; the PWM restarts automatically
ECCP1DEL: ENHANCED PWM CONTROL REGISTER
Output
should transition active and the actual time it does transition active.
W = Writable bit
‘1’ = Bit is set
mode
P1DC5
R/W-0
Table
OSC
is
20-2.
/4 (4 * T
selected
P1DC4
R/W-0
Preliminary
OSC
) cycles between the scheduled time when a PWM signal
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
P1DC3
R/W-0
While the PWM Steering mode is active, the
CCP1M<1:0> bits (CCP1CON<1:0>) select the PWM
output polarity for the P1<D:A> pins.
The PWM auto-shutdown operation also applies to the
PWM Steering mode, as described in Section 20.4.4
“Enhanced
auto-shutdown event will only affect pins that have
PWM outputs enabled.
P1DC2
R/W-0
PWM
Auto-shutdown
 2011 Microchip Technology Inc.
x = Bit is unknown
P1DC1
R/W-0
mode” .
P1DC0
R/W-0
bit 0
An