PIC18F46K80-I/ML Microchip Technology Inc., PIC18F46K80-I/ML Datasheet - Page 228

• Manufacturer Part Number: PIC18F46K80-I/ML
• Description: 44 QFN 8X8X0.9MM TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F46K80-I/ML

• A/d Inputs: 11-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 35
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin QFN
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F66K80 FAMILY
15.2
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2 to PR2 match) provides
the input for the four-bit output counter/postscaler. This
counter generates the TMR2 match interrupt flag, which
is latched in TMR2IF (PIR1<1>). The interrupt is enabled
by setting the TMR2 Match Interrupt Enable bit, TMR2IE
(PIE1<1>).
A range of 16 postscaler options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS<3:0> (T2CON<6:3>).
FIGURE 15-1:
TABLE 15-1:
DS39977C-page 228
INTCON
PIR1
PIE1
IPR1
TMR2
T2CON
PR2
PMD1
Legend: — = unimplemented, read as ‘ 0 ’. Shaded cells are not used by the Timer2 module.
Name
T2OUTPS<3:0>
T2CKPS<1:0>
F
OSC
/4
Timer2 Interrupt
Timer2 Register
Timer2 Period Register
GIE/GIEH
PSPMD
PSPIF
PSPIE
PSPIP
Bit 7
—
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
TIMER2 BLOCK DIAGRAM
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
PEIE/GIEL
CTMUMD
Internal Data Bus
1:1, 1:4, 1:16
2
Prescaler
ADIE
ADIP
ADIF
Bit 6
TMR0IE
ADCMD
RC1IE
RC1IP
RC1IF
Bit 5
4
TMR2
Preliminary
Reset
8
TMR4MD
INT0IE
TX1IF
TX1IE
TX1IP
Bit 4
15.3
The unscaled output of TMR2 is available primarily to
the ECCP modules, where it is used as a time base for
operations in PWM mode.
Timer2 can optionally be used as the shift clock source
for the MSSP module operating in SPI mode.
Additional information is provided in
“Master Synchronous Serial Port (MSSP) Module”
Comparator
1:1 to 1:16
Postscaler
TMR3MD
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
8
TMR2/PR2
Match
Timer2 Output
TMR1GIF
TMR1GIE
TMR1GIP
TMR2MD
TMR2ON
TMR0IF
Bit 2
 2011 Microchip Technology Inc.
PR2
8
T2CKPS1
TMR1MD
TMR2IF
TMR2IE
TMR2IP
INT0IF
Bit 1
Set TMR2IF
TMR2 Output
(to PWM or MSSP)
Section 21.0
T2CKPS0
TMR0MD
TMR1IF
TMR1IE
TMR1IP
RBIF
Bit 0
.