PIC16F631-I/P Microchip Technology Inc., PIC16F631-I/P Datasheet - Page 177

• Manufacturer Part Number: PIC16F631-I/P
• Description: MCU, 8-Bit, 1KW Flash, 64 RAM, 18 I/O, PDIP-20
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F631-I/P

• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 18
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 20-pin PDIP
• Programmable Memory: 1.75K Bytes
• Ram Size: 64 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

13.0
The Synchronous Serial Port (SSP) module is a serial
interface used to communicate with other peripheral or
microcontroller devices. These peripheral devices
may be serial EEPROMs, shift registers, display
drivers, A/D converters, etc. The SSP module can
operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I
Refer to Application Note AN578, “Use of the SSP
Module in the Multi-Master Environment” (DS00578).
13.1
This section contains register definitions and operational
characteristics of the SPI module.
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. To accomplish
communication, typically three pins are used:
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Serial Clock (SCK)
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS)
© 2007 Microchip Technology Inc.
Note 1: When the SPI is in Slave mode with SS
2: If the SPI is used in Slave mode with
3: When the SPI is in Slave mode with SS
SSP MODULE OVERVIEW
SPI Mode
pin control enabled (SSPM<3:0> bits of
the SSPCON register = 0100), the SPI
module will reset if the SS pin is set to
V
CKE = 1, then the SS pin control must be
enabled.
pin control enabled (SSPM<3:0> bits of
the SSPCON register = 0100), the state
of the SS pin can affect the state read
back from the TRISC<4> bit. The
peripheral OE signal from the SSP
module into PORTC controls the state that
is read back from the TRISC<4> bit (see
Section 17.0
Specifications”
PORTC). If read-write-modify instructions,
such as BSF, are performed on the
TRISC register while the SS pin is high,
this will cause the TRISC<7> bit to be set,
thus disabling the SDO output.
DD
.
2
C
™
for
)
PIC16F631/677/685/687/689/690
information
“Electrical
on
FIGURE 13-1:
SDI/SDA
SCK/
SDO
SCL
SS
Peripheral OE
Read
SS Control
Select
TRISB<6>
Edge
bit 0
Enable
Select
Edge
SSPBUF Reg
SSP BLOCK DIAGRAM
(SPI MODE)
SSPSR Reg
SSPM<3:0>
Clock Select
4
2
DS41262D-page 175
Write
Prescaler
4, 16, 64
Clock
Shift
TMR2 Output
Data Bus
Internal
2
T
CY