FIN1532M Fairchild Semiconductor, FIN1532M Datasheet - Page 3

• Manufacturer Part Number: FIN1532M
• Description: IC RCVR QUAD 5V HS LVDS 16SOIC
• Manufacturer: Fairchild Semiconductor
• Type: Receiverr

Specifications of FIN1532M

• Number Of Drivers/receivers: 0/4
• Protocol: LVDS
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Data Rate: 400 Mbps
• Interface: EIA/TIA-644
• Minimum Operating Temperature: - 65 C
• Supply Current: 17 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FIN1532M_NL; FIN1532M_NL

t
t
t
t
t
t
t
t
f
t
t
t
t
PLH
PHL
TLH
THL
SK(P)
SK(LH)
SK(HL)
SK(PP)
MAX
ZH
ZL
HZ
LZ
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Note 3: All typical values are at T
Note 4: t
tion.
Note 5: t
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6: f
All channels switching in phase.
Note A: All input pulses have frequency
Note B: C
Symbol
,
SK(LH)
SK(PP)
MAX
L
includes all probe and jig capacitances
Propagation Delay
LOW-to-HIGH
Propagation Delay
HIGH-to-LOW
Output Rise Time (20% to 80%)
Output Fall Time (80% to 20%)
Pulse Skew |t
Channel-to-Channel Skew
(Note 4)
Part-to-Part Skew (Note 5)
Maximum Operating Frequency
(Note 6)
LVTTL Output Enable Time from Z to HIGH R
LVTTL Output Enable Time from Z to LOW See Figure 3 and Figure 4
LVTTL Output Disable Time from HIGH to Z
LVTTL Output Disable Time from LOW to Z
Criteria: Input t
, t
is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
SK(HL)
is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direc-
FIGURE 1. Differential Receiver Voltage Definitions and Propagation Delay
PLH
R
Parameter
t
- t
F
A
PHL
1 ns, V
25 C and with V
|
10 MHz, t
ID
300 mV, (1.05V to 1.35V pp), 50% duty cycle; Output duty cycle 40% to 60%, V
R
CC
or t
F
5V.
1 ns
|V
See Figure 1 and Figure 2
R
See Figure 1 and Figure 2
L
L
ID
|
1k , C
1k , C
400 mV, C
Test Conditions
L
L
3
10 pF,
10 pF,
L
10 pF, R
L
1k
Min
200
1.0
1.0
(Note 3)
Typ
260
2.0
2.0
1.3
1.1
0.2
0.1
8
8
4
4
OL
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0.5V, V
Max
12.0
12.0
3.0
3.0
0.5
0.3
1.0
8.0
8.0
OH
2.4V.
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns