DS26518GN+ Maxim Integrated Products, DS26518GN+ Datasheet - Page 5

• Manufacturer Part Number: DS26518GN+
• Description: IC TXRX T1/E1/J1 8PORT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26518GN+

• Number Of Drivers/receivers: 8/8
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS26518 8-Port T1/E1/J1 Transceiver
LIST OF FIGURES
Figure 7-1. Block Diagram ......................................................................................................................................... 18
Figure 7-2. Detailed Block Diagram........................................................................................................................... 19
Figure 9-1. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 0 ............................................... 29
Figure 9-2. SPI Serial Port Access for Read Mode, SPI_CPOL = 1, SPI_CPHA = 0 ............................................... 29
Figure 9-3. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 1 ............................................... 29
Figure 9-4. SPI Serial Port Access for Read Mode, SPI_CPOL = 1, SPI_CPHA = 1 ............................................... 29
Figure 9-5. SPI Serial Port Access for Write Mode, SPI_CPOL = 0, SPI_CPHA = 0 ............................................... 30
Figure 9-6. SPI Serial Port Access for Write Mode, SPI_CPOL = 1, SPI_CPHA = 0 ............................................... 30
Figure 9-7. SPI Serial Port Access for Write Mode, SPI_CPOL = 0, SPI_CPHA = 1 ............................................... 30
Figure 9-8. SPI Serial Port Access for Write Mode, SPI_CPOL = 1, SPI_CPHA = 1 ............................................... 30
Figure 9-9. Backplane Clock Generation................................................................................................................... 31
Figure 9-10. Device Interrupt Information Flow Diagram........................................................................................... 35
Figure 9-11. IBO Multiplexer Equivalent Circuit—4.096MHz .................................................................................... 40
Figure 9-12. IBO Multiplexer Equivalent Circuit—8.192MHz .................................................................................... 41
Figure 9-13. IBO Multiplexer Equivalent Circuit—16.384MHz .................................................................................. 42
Figure 9-14. RSYNCn Input in H.100 (CT Bus) Mode............................................................................................... 46
Figure 9-15. TSSYNCIOn (Input Mode) Input in H.100 (CT Bus) Mode ................................................................... 46
Figure 9-16. CRC-4 Recalculate Method .................................................................................................................. 70
Figure 9-17. HDLC Message Receive Example........................................................................................................ 76
Figure 9-18. HDLC Message Transmit Example....................................................................................................... 78
Figure 9-19. Network Connection—Longitudinal Protection ..................................................................................... 81
Figure 9-20. T1/J1 Transmit Pulse Templates .......................................................................................................... 84
Figure 9-21. E1 Transmit Pulse Templates ............................................................................................................... 85
Figure 9-22. Receive LIU Termination Options ......................................................................................................... 87
Figure 9-23. Typical Monitor Application ................................................................................................................... 88
Figure 9-24. HPS Block Diagram............................................................................................................................... 90
Figure 9-25. Jitter Attenuation ................................................................................................................................... 91
Figure 9-26. Loopback Diagram ................................................................................................................................ 92
Figure 9-27. Analog Loopback................................................................................................................................... 92
Figure 9-28. Local Loopback ..................................................................................................................................... 93
Figure 9-29. Remote Loopback 2 .............................................................................................................................. 93
Figure 9-30. Dual Loopback ...................................................................................................................................... 94
Figure 11-1. T1 Receive-Side D4 Timing ................................................................................................................ 245
Figure 11-2. T1 Receive-Side ESF Timing.............................................................................................................. 245
Figure 11-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled)............................................................... 246
Figure 11-4. T1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled).............................................. 246
Figure 11-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled).............................................. 247
Figure 11-6. T1 Receive-Side Interleave Bus Operation—BYTE Mode.................................................................. 248
Figure 11-7. T1 Receive-Side Interleave Bus Operation—FRAME Mode .............................................................. 249
Figure 11-8. T1 Receive-Side RCHCLKn Gapped Mode During F-Bit.................................................................... 249
Figure 11-9. T1 Transmit-Side D4 Timing ............................................................................................................... 250
Figure 11-10. T1 Transmit-Side ESF Timing........................................................................................................... 250
Figure 11-11. T1 Transmit-Side Boundary Timing (Elastic Store Disabled)............................................................ 251
Figure 11-12. T1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)........................................... 251
Figure 11-13. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)........................................... 252
Figure 11-14. T1 Transmit-Side Interleave Bus Operation—BYTE Mode............................................................... 253
Figure 11-15. T1 Transmit-Side Interleave Bus Operation—FRAME Mode ........................................................... 254
Figure 11-16. T1 Transmit-Side TCHCLKn Gapped Mode During F-Bit ................................................................. 254
Figure 11-17. E1 Receive-Side Timing.................................................................................................................... 255
5 of 286