DS26518GN+ Maxim Integrated Products, DS26518GN+ Datasheet - Page 25

• Manufacturer Part Number: DS26518GN+
• Description: IC TXRX T1/E1/J1 8PORT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26518GN+

• Number Of Drivers/receivers: 8/8
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

D[5]/SPI_SWAP
D[6]/SPI_CPHA
D[7]/SPI_CPOL
D[2]/SPI_SCLK
D[1]/SPI_MOSI
D[0]/SPI_MISO
NAME
RDB/
CSB
DSB
A12
A11
A10
D[4]
D[3]
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
C10
PIN
B10
A10
C8
C9
D9
N9
M9
R8
N8
M8
A8
B8
F8
B9
A9
E9
F9
T9
T8
P8
T7
L9
Output
Output
Output
Output
Output
Output
Output
Ouput
TYPE
Input/
Input/
Input/
Input/
Input/
Input/
Input/
Input/
Input
Input
Input
MICROPROCESSOR INTERFACE
Address [12:0]. This bus selects a specific register in the DS26518 during
read/write access. A12 is the MSB and A0 is the LSB.
Data [7]/SPI Interface Clock Polarity
D[7]: Bit 7 of the 16-bit or 8-bit data bus used to input data during register writes
and data outputs during register reads. Not driven when CSB = 1.
SPI_CPOL: This signal selects the clock polarity when SPI_SEL = 1. See Section
9.1.2
Data [6]/SPI Interface Clock Phase
D[6]: Bit 6 of the 16-bit or 8-bit data bus used to input data during register writes
and data outputs during register reads. Not driven when CSB = 1.
SPI_CPHA: This signal selects the clock phase when SPI_SEL = 1. See Section
9.1.2
Data [5]/SPI Bit Order Swap
D[5]: Bit 5 of the 16-bit or 8-bit data bus used to input data during register writes
and data outputs during register reads. Not driven when CSB = 1.
SPI_SWAP: This signal is active when SPI_SEL = 1. The address and data bit
order is swapped when SPI_SWAP is high. The R/W and B bit positions are
never changed in the control word.
Data [4]. Bit 4 of the 8-bit data bus used to input data during register writes and
data outputs during register reads. Not driven when CSB = 1.
Data [3]. Bit 3 of the 8-bit data bus used to input data during register writes and
data outputs during register reads. Not driven when CSB = 1.
Data [2]/SPI Serial Interface Clock
D[2]: Bit 2 of the 8-bit data bus used to input data during register writes and data
outputs during register reads. Not driven when CSB = 1.
SPI_SCLK: SPI Serial Clock Input when SPI_SEL = 1.
Data [1]/SPI Serial Interface Data Master Out-Slave In
D[1]: Bit 1 of the 8-bit data bus used to input data during register writes, and data
outputs during register reads. Not driven when CSB = 1.
SPI_MOSI: SPI Serial Data Input (Master Out-Slave In) when SPI_SEL = 1.
Data [0]/SPI Serial Interface Data Master In-Slave Out
D[0]: Bit 0 of the 8-bit data bus used to input data during register writes and data
outputs during register reads. Not driven when CSB = 1.
SPI_MISO: SPI Serial Data Output (Master In-Slave Out) when SPI_SEL = 1.
Chip-Select Bar. This active-low signal is used to qualify register read/write
accesses. The RDB/DSB and WRB signals are qualified with CSB.
Read-Data Bar/Data-Strobe Bar. This active-low signal along with CSB qualifies
read access to one of the DS26518 registers. The DS26518 drives the data bus
with the contents of the addressed register while RDB and CSB are low.
0 = LSB is transmitted and received first.
1 = MSB is transmitted and received first.
for detailed timing and functionality information. Default setting is low.
for detailed timing and functionality information. Default setting is low.
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FUNCTION
DS26518 8-Port T1/E1/J1 Transceiver