IDT82V2048EBBG IDT, Integrated Device Technology Inc, IDT82V2048EBBG Datasheet - Page 25

• Manufacturer Part Number: IDT82V2048EBBG
• Description: IC LINE INTERFACE UNIT 208-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Line Interface Units (LIUs)r

Specifications of IDT82V2048EBBG

• Protocol: E1
• Voltage - Supply: 3.13 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 208-PBGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 800-1704; 82V2048EBBG

OCTAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
3.5
3.5.1
nal level and pulse density of the received signal on RTIPn and RRINGn.
when the signal level is less than Q dB below nominal for N consecutive
pulse intervals. Here N is defined by LAC bit (MAINT0, 0AH...). LOS will be
declared by pulling LOSn pin to high (LOS=1) and LOS interrupt will be gen-
erated if it is not masked.
when the signal level is greater than P dB below nominal and has an aver-
age pulse density of at least 12.5% for M consecutive pulse intervals, start-
ing with the receipt of a pulse. Here M is defined by LAC bit (MAINT0,
0AH...). LOS status is cleared by pulling LOSn pin to low.
Table-13 LOS Declare and Clear Criteria, Adaptive Equalizer Disabled
The Loss of Signal Detector monitors the amplitude of the incoming sig-
• LOS declare (LOS=1)
A LOS is detected when the incoming signal has “no transitions”, i.e.,
• LOS clear (LOS=0)
The LOS is cleared when the incoming signal has “transitions”, i.e.,
(observing windows= M)
1=T1/J1
T1E1
0=E1
LOS AND AIS DETECTION
LOS DETECTION
density=OK
signal level>P
Control bit
Figure-14 LOS Declare and Clear
0=T1.231
1=I.431
0=G.775
1=I.431/ETSI
LAC
Level < 800 mVpp
N=175 bits
Level < 800 mVpp
N=1544 bits
Level < 800 mVpp
N=32 bits
Level < 800 mVpp
N=2048 bits
LOS=1
LOS=0
signal level<Q
(observing windows= N)
LOS declare threshold
25
800 mVpp, while P=Q+200 mVpp (200 mVpp is the LOS level detect hys-
teresis).
LOS[4:0] bit (RCF1, 08H...), while P=Q+4 dB (4 dB is the LOS level detect
hysteresis). Refer to Table 34, “RCF1: Receiver Configuration Register 1,”
on page 43 for LOS[4:0] bit (RCF1, 08H...) values available.
G.775 and ETSI 300233/I.431 for E1 mode. The criteria can be selected
by LAC bit (MAINT0, 0AH...) and T1E1 bit (GCF0, 40H).
both with and without the Adaptive Equalizer enabled.
tion” at the RTIPn/RRINGn side and output recovery clock (but the quality
of the output clock can not be guaranteed when the input level is lower than
the maximum receive sensitivity) when AISE bit (MAINT0, 0AH...) is 0; or
output All Ones as AIS when AISE bit (MAINT0, 0AH...) is 1. In this case
RCLKn output is replaced by MCLK.
ATAO bit (MAINT0, 0AH...) is 1. The All Ones pattern uses MCLK as the
reference clock.
• LOS detect level threshold
• Criteria for declare and clear of a LOS detect
The detection supports the ANSI T1.231 and I.431 for T1/J1 mode and
Table-13
• All Ones output during LOS
On the system side, the RDPn/RDNn will reflect the input pulse “transi-
On the line side, the TTIPn/TRINGn will output All Ones as AIS when
LOS indicator is always active for all kinds of loopback modes.
With the Adaptive Equalizer off, the amplitude threshold Q is fixed on
With the Adaptive Equalizer on, the value of Q can be selected by
and
Level > 1 Vpp
M=128 bits
12.5% mark density
<100 consecutive zeroes
Level > 1 Vpp
M=128 bits
12.5% mark density
<100 consecutive zeroes
Level > 1 Vpp
M=32 bits
12.5% mark density
<16 consecutive zeroes
Level > 1 Vpp
M=32 bits
12.5% mark density
<16 consecutive zeroes
Table-14
summarize LOS declare and clear criteria for
LOS clear threshold
TEMPERATURE RANGES
INDUSTRIAL