PIC18F45K22-I/P Microchip Technology Inc., PIC18F45K22-I/P Datasheet - Page 97
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC18F45K22-I/P
Manufacturer Part Number
PIC18F45K22-I/P
Description
40 PDIP .600in TUBE, 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F45K22-IP.pdf
(496 pages)
Specifications of PIC18F45K22-I/P
A/d Inputs
28-Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
35
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
3-8-bit, 4-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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REGISTER 6-1:
2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
S = Bit can be set by software, but not cleared
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
EEPGD
R/W-x
When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the
error condition.
EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access Flash program memory
0 = Access data EEPROM memory
CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access Configuration registers
0 = Access Flash program or data EEPROM memory
Unimplemented: Read as ‘0’
FREE: Flash Row (Block) Erase Enable bit
1 = Erase the program memory block addressed by TBLPTR on the next WR command
0 = Perform write-only
WRERR: Flash Program/Data EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal
0 = The write operation completed
WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM
WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
0 = Write cycle to the EEPROM is complete
RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared by hardware. The RD bit can only
0 = Does not initiate an EEPROM read
CFGS
R/W-x
(cleared by completion of erase operation)
operation, or an improper write attempt)
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) by software.)
be set (not cleared) by software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)
EECON1: DATA EEPROM CONTROL 1 REGISTER
W = Writable bit
‘1’ = Bit is set
U-0
—
R/W-0
FREE
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
WRERR
R/W-x
PIC18(L)F2X/4XK22
(1)
WREN
R/W-0
x = Bit is unknown
R/S-0
WR
DS41412D-page 97
R/S-0
RD
bit 0
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