PIC18F45K22-I/P Microchip Technology Inc., PIC18F45K22-I/P Datasheet - Page 120
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PIC18F45K22-I/P
Manufacturer Part Number
PIC18F45K22-I/P
Description
40 PDIP .600in TUBE, 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F45K22-IP.pdf
(496 pages)
Specifications of PIC18F45K22-I/P
A/d Inputs
28-Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
35
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
3-8-bit, 4-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC18(L)F2X/4XK22
REGISTER 9-6:
DS41412D-page 120
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SSP2IF
R/W-0
SSP2IF: Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
BCL2IF: MSSP2 Bus Collision Interrupt Flag bit
1 = A bus collision has occurred while the SSP2 module configured in I
0 = No bus collision occurred
RC2IF: EUSART2 Receive Interrupt Flag bit
1 = The EUSART2 receive buffer, RCREG2, is full (cleared by reading RCREG2)
0 = The EUSART2 receive buffer is empty
TX2IF: EUSART2 Transmit Interrupt Flag bit
1 = The EUSART2 transmit buffer, TXREG2, is empty (cleared by writing TXREG2)
0 = The EUSART2 transmit buffer is full
CTMUIF: CTMU Interrupt Flag bit
1 = CTMU interrupt occurred (must be cleared in software)
0 = No CTMU interrupt occurred
TMR5GIF: TMR5 Gate Interrupt Flag bits
1 = TMR gate interrupt occurred (must be cleared in software)
0 = No TMR gate occurred
TMR3GIF: TMR3 Gate Interrupt Flag bits
1 = TMR gate interrupt occurred (must be cleared in software)
0 = No TMR gate occurred
TMR1GIF: TMR1 Gate Interrupt Flag bits
1 = TMR gate interrupt occurred (must be cleared in software)
0 = No TMR gate occurred
BCL2IF
R/W-0
(must be cleared in software)
PIR3: PERIPHERAL INTERRUPT (FLAG) REGISTER 3
W = Writable bit
‘1’ = Bit is set
RC2IF
R/W-0
R/W-0
TX2IF
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CTMUIF
R/W-0
TMR5GIF
R/W-0
2010 Microchip Technology Inc.
x = Bit is unknown
2
C master was transmitting
TMR3GIF
R/W-0
TMR1GIF
R/W-0
bit 0
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