DSPIC30F6010A-30I/PF Microchip Technology Inc., DSPIC30F6010A-30I/PF Datasheet - Page 25
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DSPIC30F6010A-30I/PF
Manufacturer Part Number
DSPIC30F6010A-30I/PF
Description
16 BIT MCU/DSP 80LD 30MIPS 144 KB FLASH
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC30F6010A-30IPF.pdf
(236 pages)
Specifications of DSPIC30F6010A-30I/PF
A/d Inputs
16-Channels, 10-Bit
Cpu Speed
30 MIPS
Eeprom Memory
4K Bytes
Input Output
68
Interface
CAN, I2C, SPI, UART/USART
Ios
68
Memory Type
Flash
Number Of Bits
16
Package Type
80-pin TQFP
Programmable Memory
144K Bytes
Ram Size
8K Bytes
Timers
5-16-bit, 2-32-bit
Voltage, Range
2.5-5.5
Lead Free Status / Rohs Status
RoHS Compliant part
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3.1.1
This architecture fetches 24-bit wide program memory.
Consequently, instructions are always aligned. How-
ever, as the architecture is modified Harvard, data can
also be present in program space.
There are two methods by which program space can
be accessed; via special table instructions, or through
the remapping of a 16K word program space page into
the upper half of data space (see Section 3.1.2 “Data
Access From Program Memory Using Program
Space Visibility”). The TBLRDL and TBLWTL instruc-
tions offer a direct method of reading or writing the least
significant word of any address within program space,
without going through data space. The TBLRDH and
TBLWTH instructions are the only method whereby the
upper 8 bits of a program space word can be accessed
as data.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit
word-wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the lsw, and TBLRDH
and TBLWTH access the space which contains the
MSB.
Figure 3-2 shows how the EA is created for table oper-
ations and data space accesses (PSV = 1). Here,
P<23:0> refers to a program space word, whereas
D<15:0> refers to a data space word.
FIGURE 3-3:
© 2006 Microchip Technology Inc.
Program Memory
‘Phantom’ Byte
(Read as ‘0’).
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
PC Address
0x000004
0x000006
0x000002
0x000000
PROGRAM DATA TABLE ACCESS (LEAST SIGNIFICANT WORD)
00000000
00000000
00000000
00000000
23
TBLRDL.W
16
dsPIC30F6010A/6015
A set of table instructions are provided to move byte or
word-sized data to and from program space.
1.
2.
3.
4.
TBLRDL: Table Read Low
Word: Read the least significant word of the
program address;
P<15:0> maps to D<15:0>.
Byte: Read one of the Least Significant Bytes of
the program address;
P<7:0> maps to the destination byte when byte
select = 0;
P<15:8> maps to the destination byte when byte
select = 1.
TBLWTL: Table Write Low (refer to Section 6.0
“Flash Program Memory” for details on Flash
Programming).
TBLRDH: Table Read High
Word: Read the most significant word of the
program address;
P<23:16> maps to D<7:0>; D<15:8> always
be = 0.
Byte: Read one of the Most Significant Bytes of
the program address;
P<23:16> maps to the destination byte when
byte select = 0;
The destination byte will always be = 0 when
byte select = 1.
TBLWTH: Table Write High (refer to Section 6.0
“Flash Program Memory” for details on Flash
Programming).
TBLRDL.B (Wn<0> = 1)
8
TBLRDL.B (Wn<0> = 0)
0
DS70150B-page 23
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