DSPIC30F6010A-30I/PF Microchip Technology Inc., DSPIC30F6010A-30I/PF Datasheet - Page 231
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
DSPIC30F6010A-30I/PF
Manufacturer Part Number
DSPIC30F6010A-30I/PF
Description
16 BIT MCU/DSP 80LD 30MIPS 144 KB FLASH
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC30F6010A-30IPF.pdf
(236 pages)
Specifications of DSPIC30F6010A-30I/PF
A/d Inputs
16-Channels, 10-Bit
Cpu Speed
30 MIPS
Eeprom Memory
4K Bytes
Input Output
68
Interface
CAN, I2C, SPI, UART/USART
Ios
68
Memory Type
Flash
Number Of Bits
16
Package Type
80-pin TQFP
Programmable Memory
144K Bytes
Ram Size
8K Bytes
Timers
5-16-bit, 2-32-bit
Voltage, Range
2.5-5.5
Lead Free Status / Rohs Status
RoHS Compliant part
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6010A-30I/PF
Manufacturer:
AD
Quantity:
2 100
Company:
Part Number:
DSPIC30F6010A-30I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
Timing Requirements
Timing Specifications
Traps .................................................................................. 41
U
UART
© 2006 Microchip Technology Inc.
SPI Master Mode (CKE = 1) .................................... 201
SPI Slave Mode (CKE = 0) ...................................... 202
SPI Slave Mode (CKE = 1) ...................................... 203
Time-out Sequence on Power-up (MCLR
Time-out Sequence on Power-up (MCLR
Time-out Sequence on Power-up (MCLR
TimerQ (QEI Module) External Clock ...................... 194
Timer1, 2, 3, 4, 5 External Clock .............................. 192
10-bit High-Speed A/D Conversion (CHPS = 01,
10-bit High-Speed A/D Conversion (CHPS = 01,
Input Capture ........................................................... 195
Band Gap Start-up Time Requirements ................... 191
CAN I/O Requirements ............................................ 209
CLKOUT and I/O Characteristics ............................. 189
CLKOUT and I/O Requirements .............................. 189
External Clock Requirements .................................. 185
Internal Clock Examples .......................................... 187
I
I
Motor Control PWM Requirements .......................... 197
Output Compare Requirements ............................... 195
PLL Clock ................................................................. 186
PLL Jitter .................................................................. 186
QEI External Clock Requirements ........................... 194
QEI Index Pulse Requirements ................................ 199
Quadrature Decoder Requirements ......................... 198
Reset, Watchdog Timer, Oscillator Start-up
Simple OC/PWM Mode Requirements .................... 196
SPI Master Mode (CKE = 0) Requirements ............. 200
SPI Master Mode (CKE = 1) Requirements ............. 201
SPI Slave Mode (CKE = 0) Requirements ............... 202
SPI Slave Mode (CKE = 1) Requirements ............... 203
Timer1 External Clock Requirements ...................... 192
Timer2 and Timer4 External Clock Requirements ... 193
Timer3 and Timer5 External Clock Requirements ... 193
10-bit High-Speed A/D ............................................. 210
10-bit High-Speed A/D Conversion Requirements .. 214
Hard and Soft ............................................................. 42
Sources ...................................................................... 41
Vectors ....................................................................... 42
Address Detect Mode .............................................. 119
Auto-Baud Support .................................................. 120
Baud Rate Generator (BRG) .................................... 119
Disabling .................................................................. 117
Enabling and Setup .................................................. 117
Loopback Mode ....................................................... 119
Module Overview ..................................................... 115
Operation During CPU Sleep and Idle Modes ......... 120
Receiving Data ......................................................... 118
2
2
C Bus Data Requirements (Master Mode) ............ 206
C Bus Data Requirements (Slave Mode) .............. 208
Not Tied to V
Not Tied to V
Tied to V
SIMSAM = 0, ASAM = 0, SSRC = 000) ........... 212
SIMSAM = 0, ASAM = 1, SSRC = 111,
SAMC = 00001) ............................................... 213
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 191
In 8-bit or 9-bit Data Mode ............................... 118
Interrupt ........................................................... 118
Receive Buffer (UxRXB) .................................. 118
DD
) ..................................................... 154
DD
DD
), Case 1 ................................. 154
), Case 2 ................................. 155
dsPIC30F6010A/6015
Unit ID Locations ............................................................. 147
Universal Asynchronous Receiver Transmitter
W
Wake-up from Sleep ........................................................ 147
Wake-up from Sleep and Idle ............................................ 43
Watchdog Timer (WDT) ........................................... 147, 158
WWW Address ................................................................ 231
WWW, On-Line Support ...................................................... 5
Z
16-bit Up/Down Position Counter Mode ............................ 88
Reception Error Handling ........................................ 118
Setting Up Data, Parity and Stop Bit Selections ...... 117
Transmitting Data .................................................... 117
UART1 Register Map .............................................. 121
UART2 Register Map .............................................. 121
Module (UART) ........................................................ 115
Enabling and Disabling ............................................ 158
Operation ................................................................. 158
Count Direction Status ............................................... 88
Error Checking ........................................................... 88
Framing Error (FERR) ..................................... 119
Idle Status ....................................................... 119
Parity Error (PERR) ......................................... 119
Receive Break ................................................. 119
Receive Buffer Overrun Error (OERR Bit) ....... 118
In 8-bit Data Mode ........................................... 117
In 9-bit Data Mode ........................................... 117
Interrupt ........................................................... 118
Transmit Break ................................................ 118
Transmit Buffer (UxTXB) ................................. 117
DS70150B-page 229