DP83849CVS/NOPB National Semiconductor, DP83849CVS/NOPB Datasheet - Page 10

• Manufacturer Part Number: DP83849CVS/NOPB
• Description: IC TXRX ETHERNET PHY DUAL 80TQFP
• Manufacturer: National Semiconductor
• Type: Transceiverr

Specifications of DP83849CVS/NOPB

• Number Of Drivers/receivers: 2/2
• Protocol: Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP, 80-VQFP
• Data Rate: 100Mbps
• Supply Voltage Range: 3V To 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 80
• Operating Temperature Range: 0°C To +70°C
• Msl: MSL 3 - 168 Hours
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Data Rate Max: 10Mbps
• For Use With: DP83849CVS-EVK - BOARD EVALUATION DP83849CVS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DP83849CVS; *DP83849CVS/NOPB; DP83849CVS

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RX_CLK_A
RX_CLK_B
RX_DV_A
RX_DV_B
RX_ER_A
RX_ER_B
RXD[3:0]_A
RXD[3:0]_B
CRS_A/CRS_DV_A
CRS_B/CRS_DV_B
COL_A
COL_B
Signal Name
Type
O
O
O
O
O
O
53,56,57,58
9,8,5,4
Pin #
79
63
80
62
60
61
59
2
1
3
MII RECEIVE CLOCK: Provides the 25 MHz recovered receive
clocks for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode.
Unused in RMII mode. The device uses the X1 reference clock input
as the 50 MHz reference for both transmit and receive.
SNI RECEIVE CLOCK: Provides the 10 MHz recovered receive
clocks for 10 Mb/s SNI mode.
MII RECEIVE DATA VALID: Asserted high to indicate that valid data
is present on the corresponding RXD[3:0].
RMII RECEIVE DATA VALID: Asserted high to indicate that valid
data is present on the corresponding RXD[1:0]. This signal is not re-
quired in RMII mode, since CRS_DV includes the RX_DV signal, but
is provided to allow simpler recovery of the Receive data.
This pin is not used in SNI mode.
MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to
indicate that an invalid symbol has been detected within a received
packet in 100 Mb/s mode.
RMII RECEIVE ERROR: Asserted high synchronously to X1 whenev-
er an invalid symbol is detected, and CRS_DV is asserted in 100 Mb/s
mode. This pin is also asserted on detection of a False Carrier event.
This pin is not required to be used by a MAC in RMII mode, since the
Phy is required to corrupt data on a receive error.
This pin is not used in SNI mode.
MII RECEIVE DATA: Nibble wide receive data signals driven syn-
chronously to the RX_CLK, 25 MHz for 100 Mb/s mode, 2.5 MHz for
10 Mb/s mode). RXD[3:0] signals contain valid data when RX_DV is
asserted.
RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven
synchronously to the X1 clock, 50 MHz.
SNI RECEIVE DATA: Receive data signal, RXD_0, driven synchro-
nously to the RX_CLK. RXD_0 contains valid data when CRS is as-
serted. RXD[3:1] are not used in this mode.
MII CARRIER SENSE: Asserted high to indicate the receive medium
is non-idle.
RMII CARRIER SENSE/RECEIVE DATA VALID: This signal com-
bines the RMII Carrier and Receive Data Valid indications. For a de-
tailed description of this signal, see the RMII Specification.
SNI CARRIER SENSE: Asserted high to indicate the receive medium
is non-idle. It is used to frame valid receive data on the RXD_0 signal.
MII COLLISION DETECT: Asserted high to indicate detection of a
collision condition (simultaneous transmit and receive activity) in 10
Mb/s and 100 Mb/s Half Duplex Modes.
While in 10BASE-T Half Duplex mode with heartbeat enabled this pin
is also asserted for a duration of approximately 1 s at the end of
transmission to indicate heartbeat (SQE test).
In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this signal is
always logic 0. There is no heartbeat function during 10 Mb/s full du-
plex operation.
RMII COLLISION DETECT: Per the RMII Specification, no COL sig-
nal is required. The MAC will recover CRS from the CRS_DV signal
and use that along with its TX_EN signal to determine collision.
SNI COLLISION DETECT: Asserted high to indicate detection of a
collision condition (simultaneous transmit and receive activity) in 10
Mb/s SNI mode.
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Description