AD9954YSVZ Analog Devices Inc, AD9954YSVZ Datasheet - Page 6

• Manufacturer Part Number: AD9954YSVZ
• Description: IC DDS DAC 14BIT 1.8V 48-TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9954YSVZ

• Resolution (bits): 14 b
• Master Fclk: 400MHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 1.71 V ~ 1.96 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Data Rate: 25Mbps
• Rf Ic Case Style: TQFP
• No. Of Pins: 48
• Supply Voltage Range: 1.71V To 1.89V, 3.135V To 3.465V
• Operating Temperature Range: -40°C To +105°C
• Msl: MSL 3 - 168 Hours
• Termination Type: SMD
• Rohs Compliant: Yes
• Filter Terminals: SMD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9954/PCBZ - BOARD EVAL FOR 9954
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9954
Parameter
CMOS LOGIC INPUTS
CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 1.8 V
CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 3.3 V
POWER CONSUMPTION (AVDD = DVDD = 1.8 V)
SYNCHRONIZATION FUNCTION
1
2
3
4
5
Represents the cycle-to-cycle residual jitter from the comparator alone.
Wake-up time refers to the recovery from analog power-down modes (see section on Power-Down Modes of Operation). The primary limiting factor is the settling time of the PLL
multiplier in the reference circuitry. The wake-up time assumes there is no capacitor on DAC BP and that the recommended PLL loop filter values are used.
SYSCLK cycle refers to the clock frequency used on-chip to drive the DDS core. This is equal to the frequency of the reference source times the value of the PLL-based
reference clock multiplier.
SYNC_CLK = ¼ SYSCLK rate. Be sure the high speed sync enable bit, CFR2<11>, is programmed appropriately.
This parameter indicates that the digital synchronization feature cannot compensate for phase delays (timing skew) between system clock rising edges. If the system
clock edges are aligned, the synchronization function should not increase the skew between the two edges.
Logic 1 Voltage @ DVDD_I/O (Pin 43) = 1.8 V
Logic 0 Voltage @ DVDD_I/O (Pin 43) = 1.8 V
Logic 1 Voltage @ DVDD_I/O (Pin 43) = 3.3 V
Logic 0 Voltage @ DVDD_I/O (Pin 43) = 3.3 V
Logic 1 Current
Logic 0 Current
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Voltage
Logic 0 Voltage
Single-Tone Mode (Comparator Off )
With RAM or Linear Sweep Enabled
With Comparator Enabled
With RAM and Comparator Enabled
Rapid Power-Down Mode
Full-Sleep Mode
Maximum Sync Clock Rate (DVDD_I/O = 1.8 V)
Maximum Sync Clock Rate (DVDD_I/O = 3.3 V)
SYNC_CLK Alignment Resolution
4
5
Rev. B | Page 6 of 40
Temp
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Test
Level
I
I
I
I
V
V
V
V
I
I
I
I
I
I
I
I
I
I
VI
VI
Min
1.25
2.2
1.35
2.8
62.5
100
3
2
±1
Typ
162
175
180
198
150
20
Max
0.6
0.8
12
12
0.4
0.4
171
190
190
220
160
27
Unit
V
V
V
V
μA
μA
pF
V
V
V
V
mW
mW
mW
mW
mW
mW
MHz
MHz
SYSCLK
cycles