DP8522AV-25 National Semiconductor, DP8522AV-25 Datasheet - Page 7

• Manufacturer Part Number: DP8522AV-25
• Description: IC CTRLR 4M VRAM 25MHZ 68PLCC
• Manufacturer: National Semiconductor

Specifications of DP8522AV-25

• Controller Type: Video RAM Controller, Drivers
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Voltage - Supply: -
• Interface: -
• Other names: *DP8522AV-25

2 1 ADDRESS R W AND PROGRAMMING SIGNALS
2 2 VRAM CONTROL SIGNALS
R0 –10
R0 –9
C0 –10
C0 –9
B0 B1
ECAS0 –1
WIN
COLINC
(EXTNDRF)
ML
Q0–10
Q0–9
Q0–8
RAS0 –3
CAS0 –3
DT OE
2 0 Signal Descriptions
Name
Pin
DP8522A
DP8520A 21A
DP8522A
DP8520A 21A
DP8522A
DP8521A
DP8521A
applicable to all)
Device (If not
Output
Input
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
ROW ADDRESS These inputs are used to specify the row address during an
access or refresh to the VRAM or for a VRAM transfer cycle They are also used
to program the chip when ML is asserted (except R10)
COLUMN ADDRESS These inputs are used to specify the column address
during an access to the VRAM or for a VRAM transfer cycle They are also used
to program the chip when ML is asserted (except C10)
BANK SELECT Depending on programming these inputs are used to select a
group of RAS and CAS outputs to assert during an access They are also used to
program the chip when ML is asserted
ENABLE CAS These inputs are used to enable a single or group of CAS outputs
when asserted In combination with the B0 B1 and the programming bits these
inputs select which CAS output or CAS outputs will assert during an access
ECAS0 must be asserted for either CAS0 or CAS1 to assert during an access
ECAS1 must be asserted for either CAS2 or CAS3 to assert during an access
The ECAS signals can also be used to toggle a group of CAS outputs for
page nibble mode accesses They also can be used for byte write operations If
ECAS0 is negated during programming continuing to assert the ECAS0 while
negating AREQ or AREQB during an access will cause the CAS outputs to be
extended while the RAS outputs are negated (the ECASn inputs have no effect
during scrubbing refreshes)
WRITE ENABLE IN This input is used to signify a write operation to the VRAM
This input asserted will also cause CAS to delay to the next positive clock edge if
address bit C9 is asserted during programming
COLUMN INCREMENT When the address latches are used and a refresh is not
in progress this input functions as COLINC Asserting this signal causes the
column address to be incremented by one When a refresh is in progress this
signal when asserted is used to extend the refresh cycle by any number of
periods of CLK until it is negated
MODE LOAD This input signal when low enables the internal programming
register that stores the programming information
VRAM ADDRESS These outputs are the multiplexed output of the R0– 9 10
and C0 – 9 10 and form the VRAM address bus These outputs contain the
refresh address whenever a refresh is in progress They contain high capacitive
drivers with 20
ROW ADDRESS STROBES These outputs are asserted to latch the row
address contained on the outputs Q0 – 8 9 10 into the VRAM When a refresh is
in progress the RAS outputs are used to latch the refresh row address contained
on the Q0– 8 9 10 outputs in the VRAM These outputs contain high capacitive
drivers with 20
COLUMN ADDRESS STROBES These outputs are asserted to latch the
column address contained on the outputs Q0 – 8 9 10 into the VRAM These
outputs have high capacitive drivers with 20
DATA TRANSFER OUTPUT ENABLE This output transitions low before RAS
goes low and transitions high before RAS goes high during a video RAM shift
register load operation (see VSRL pin description) During normal write accesses
this output is held high and for read accesses this output is asserted after CAS is
asserted and is negated after CAS negates
7
series damping resistors
series damping resistors
Description
series damping resistors