DP8522AV-25 National Semiconductor, DP8522AV-25 Datasheet - Page 43

• Manufacturer Part Number: DP8522AV-25
• Description: IC CTRLR 4M VRAM 25MHZ 68PLCC
• Manufacturer: National Semiconductor

Specifications of DP8522AV-25

• Controller Type: Video RAM Controller, Drivers
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Voltage - Supply: -
• Interface: -
• Other names: *DP8522AV-25

10 0 Test Mode
Staggered refresh in combination with the error scrubbing
mode places the DP8520A 21A 22A in test mode In this
mode the 24-bit refresh counter is divided into a 13-bit and
11-bit counter During refreshes both counters are incre-
mented to reduce test time
11 0 VRAM Critical Timing
Parameters
The two critical timing parameters shown in Figure 53 that
must be met when controlling the access timing to a VRAM
are the row address hold time tRAH and the column ad-
dress setup time tASC Since the DP8520A 21A 22A con-
tain a precise internal delay line the values of these param-
eters can be selected at programming time These values
will also increase and decrease if DELCLK varies from
2 MHz
11 1 PROGRAMMABLE VALUES OF tRAH AND tASC
The DP8520A 21A 22A allow the values of tRAH and tASC
to be selected at programming time For each parameter
two choices can be selected tRAH the row address hold
time is measured from RAS asserted to the row address
starting to change to the column address The two choices
for tRAH are 15 ns and 25 ns programmable through ad-
dress bit C8
tASC the column address setup time is measured from the
column address valid to CAS asserted The two choices for
tASC are 0 ns and 10 ns programmable through address bit
C7
FIGURE 53 tRAH and tASC
43
11 2 CALCULATION OF tRAH AND tASC
There are two clock inputs to the DP8520A 21A 22A
These two clocks DELCLK and CLK can either be tied to-
gether to the same clock or be tied to different clocks run-
ning asynchronously at different frequencies
The clock input DELCLK controls the internal delay line
and refresh request clock DELCLK should be a multiple of
2 MHz If DELCLK is not a multiple of 2 MHz tRAH and
tASC will change The new values of tRAH and tASC can be
calculated by the following formulas
If tRAH was programmed to equal 15 ns then tRAH
30 (((DELCLK Divisor) 2 MHz (DELCLK Frequency))
If tRAH was programmed to equal 25 ns then tRAH
30 (((DELCLK Divisor) 2 MHz (DELCLK Frequency))
If tASC was programmed to equal 0 ns then tASC
((DELCLK Divisor) 2 MHz (DELCLK Frequency))
If tASC was programmed to equal 10 ns then tASC
((DELCLK Divisor) 2 MHz (DELCLK Frequency))
Since the values of tRAH and tASC are increased or de-
creased the time to CAS asserted will also increase or de-
crease These parameters can be adjusted by the following
formula
Delay to CAS
Programmed tRAH
a
a
15 ns
25 ns
e
Actual Spec
a
Actual tASC
a
TL F 9338 – A4
Actual tRAH
b
Programmed tASC
b
b
b
e
e
15 ns
15 ns
b
b
15
25
e
e
1)
1)