DP8522AV-25 National Semiconductor, DP8522AV-25 Datasheet - Page 20
DP8522AV-25
Manufacturer Part Number
DP8522AV-25
Description
IC CTRLR 4M VRAM 25MHZ 68PLCC
Manufacturer
National Semiconductor
Datasheet
1.DP8520AV-25.pdf
(70 pages)
Specifications of DP8522AV-25
Controller Type
Video RAM Controller, Drivers
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
68-LCC (J-Lead)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Current - Supply
-
Voltage - Supply
-
Interface
-
Other names
*DP8522AV-25
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5 0 Port A Wait State Support
5 3 WAIT STATE SUPPORT FOR VIDEO RAM SHIFT
REGISTER LOAD OPERATIONS FOR PORT A
If using the DP8520A 21A 22A in a system using video
VRAMs the CPU that controls loading the Video RAM shift
register must be connected to Port A The input AVSRLRQ
asserts signaling an advanced request for a Video RAM
shift register load operation Sometime later the input VSRL
asserts signifying that the transfer cycle has started and
this action causes the DT OE output to transfer low VSRL
asserting also asserts WAIT (keeps DTACK negated) and
FIGURE 18 Wait State Timing during a VRAM Transfer Cycle (WAIT
Programmed as OT WAIT Sampled at the ‘‘T3’’ Rising Clock Edge)
(Continued)
20
will then insert wait states into the transfer cycle The trans-
fer cycle is completed from either VSRL negating or four
clocks from VSRL asserting The first event of these two to
take place causes WAIT to negate (DTACK to assert) imme-
diately or one half system clock period later depending on
how the user had programmed WAIT to end (DTACK to
start) during a non-burst type of access The wait logic is
intimately connected to the DP8520A 21A 22A graphics
functions and the WAIT output functions the same as the
DT OE output (see Figure 18 )
TL F 9338– 74
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