DP83934AVQB National Semiconductor, DP83934AVQB Datasheet - Page 96

• Manufacturer Part Number: DP83934AVQB
• Description: IC CTRLR ORIENT NETWORK 160PLCC
• Manufacturer: National Semiconductor

Specifications of DP83934AVQB

• Controller Type: Network Interface Controller (NIC)
• Interface: Twisted Pair
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 140mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83934AVQB

9 0 AC and DC Specifications
Note 3 It is not necessary to meet the setup time for CS and SAS (T56 and T69) since these signals are asynchronously sampled Meeting the setup time for these
signals however makes it possible to use T60 to determine when SMACK will be asserted SAS may be asserted anytime before the next falling edge of the clock
that the CS is sampled on (as shown by specification T69) For multiple register accesses CS can be held low and SAS can be used to delimit the slave cycle
(T69a must be met in order to terminate and start another cycle) In this case SMACK will be asserted as soon as T69 timing is met
Note 4 T60 could range from 1 bus clock minimum to 5 bus clock maximum depending on what state machine the SONIC-T is in when the CS signal is asserted
This timing is not tested but is guaranteed by design This specification assumes that both T56 is met for CS and T69 is met for SAS T60 specification also
assumes that there were no wait states in the current master mode access (if CS is asserted when SONIC-T is in Master Mode) If there were wait states then it
would increase the T60 futher
Note 5 It is not necessary to meet the setup time for SAS (T69a) since this signal is asynchronously sampled Meeting the setup time for this signal however will
ensure DSACK0 1 becomes TRI-STATE (77b) and SMACK goes high (T79) at the falling edge of T1 Both CS and SAS could cause DSACK0 1 to deassert but only
SAS could cause DSACK0 1 to become TRI-STATE
ENDEC TRANSMIT TIMING
Note 1 This specification is provided for information only and is not tested
Number
T87
T88
T89
T95
T96
T97
T98
T100
T101
Transmit Clock High Time (Note 1)
Transmit Clock Low Time (Note 1)
Transmit Clock Cycle Time (Note 1)
Transmit Output Delay (Note 1)
Transmit Output Fall Time (80% to 20% Note 1)
Transmit Output Rise Time (20% to 80% Note 1)
Transmit Output Jitter (Not Shown)
Transmit Output High before Idle (Half Step)
Transmit Output Idle Time (Half Step)
Parameter
(Continued)
96
99 99
Min
200
40
40
0 5 Typ
100 01
8000
Max
55
7
7
TL F 11719 – 76
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns