DP83934AVQB National Semiconductor, DP83934AVQB Datasheet - Page 10

• Manufacturer Part Number: DP83934AVQB
• Description: IC CTRLR ORIENT NETWORK 160PLCC
• Manufacturer: National Semiconductor

Specifications of DP83934AVQB

• Controller Type: Network Interface Controller (NIC)
• Interface: Twisted Pair
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 140mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83934AVQB

BUS INTERFACE PINS (MOTOROLA MODE BMODE
USER DEFINABLE PINS
AS
MRW
INT
BR
BG
BGACK
SRW
DSACK0
DSACK1
USR0 1
Symbol
2 0 Pin Description
Driver
Type
TRI
TRI
TRI
TRI
TRI
TRI
OC
OC
Direction
I O Z
I O Z
I O Z
O Z
O Z
O Z
O Z
O Z
I
I
(Continued)
ADDRESS STROBE (AS) The falling edge indicates valid status and address The rising edge
indicates the termination of the memory cycle
MEMORY READ WRITE STROBE (MRW) When the SONIC-T has acquired the bus this signal
indicates the direction of the data transfer This signal is high during a read cycle and low during a
write cycle
INTERRUPT (INT) Indicates that an interrupt (if enabled) is pending from one of the sources
indicated by the Interrupt Status register Interrupts that are disabled in the Interrupt Mask
register will not activate this signal
BUS REQUEST (BR) The SONIC-T asserts this pin low when it attempts to gain access to the
bus When inactive this signal is at TRI-STATE
BUS GRANT (BG) This signal is a bus grant The system asserts this pin low to indicate potential
mastership of the bus
BUS GRANT ACKNOWLEDGE The SONIC-T asserts this pin low when it has determined that it
can gain ownership of the bus The SONIC-T checks the following conditions before driving
BGACK
1 BG has been received through the bus arbitration process
2 AS is deasserted indicating that the previous master has finished using the bus
3 DSACK0 and DSACK1 are deasserted indicating that the previous slave device is off the bus
4 BGACK is deasserted indicating that the previous master is off the bus
SLAVE READ WRITE (SRW) The system asserts this pin to indicate whether it will read from or
write to the SONIC-T’s registers This signal is asserted high during a read and low during a write
DATA AND SIZE ACKNOWLEDGE 0 AND 1 (DSACK0 1 BMODE
output slave acknowledge to the system when the SONIC-T registers have been accessed and
the input slave acknowledgement when the SONIC-T is busmaster When a register has been
accessed the SONIC-T drives both DSACK0 and DSACK1 pins low to terminate the slave cycle
(Note that the SONIC-T responds as a 32-bit peripheral by driving both DSACK0 and DSACK1
low but drives data only on lines D0– D15 Lines D16– D32 are driven but invalid )
When the SONIC-T is bus master it samples these pins before terminating its memory cycle
When SONIC-T is in 32-bit bus master mode both DSACK0 and DSACK1 must be asserted to
terminate the cycle However if the SONIC-T is in 16-bit bus master mode only the assertion of
DSACK1 is required to terminate the cycle These pins are sampled synchronously or
asynchronously depending on the state of the SBUS bit in the Data Configuration register (See
Section 7 3 5 for details ) Note that the SONIC-T does not allow dynamic bus sizing Bus size is
statically defined in the Data Configuration register (see Section 6 3 2)
USER DEFINE 0 1 These signals are inputs when the SONIC-T is hardware reset and are
outputs when the SONIC-T is a bus master (HLDA or BGACK asserted) When hard reset (RST)
is low these signals input directly into bits 8 and 9 of the Data Configuration Register (DCR)
respectively The levels on these pins are latched on the rising edge of RST During busmaster
operations (HLDA or BGACK is active) these pins are outputs whose levels are programmable
through bits 11 and 12 of the DCR respectively The USR0 1 pins should be pulled up to V
pulled down to ground A 4 7 k
TABLE 2-1 Pin Description (Continued)
e
1)
10
pull-up resistor is recommended
Description
e
1) These pins are the
CC
or