DP83934AVQB National Semiconductor, DP83934AVQB Datasheet - Page 58

• Manufacturer Part Number: DP83934AVQB
• Description: IC CTRLR ORIENT NETWORK 160PLCC
• Manufacturer: National Semiconductor

Specifications of DP83934AVQB

• Controller Type: Network Interface Controller (NIC)
• Interface: Twisted Pair
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 140mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83934AVQB

7 0 Bus Interface
7 3 2 Block Transfers
The SONIC-T performs block operations during all bus ac-
tions thereby providing efficient transfers to memory The
block cycle consists of three parts The first part is the bus
acquisition phase
SONIC-T gains access to the bus Once it has access of the
bus the SONIC-T enters the second phase by transferring
data to from its internal FIFOs or registers from to memory
The SONIC-T transfers data from its FIFOs in either EXACT
BLOCK mode or EMPTY FILL
EXACT BLOCK mode In this mode the number of words
(or long words) transferred during a block transfer is deter-
mined by either the Transmit or Receive FIFO thresholds
programmed in the Data Configuration Register
EMPTY FILL mode In this mode the DMA completely fills
the Transmit FIFO during transmission or completely emp-
ties the Receive FIFO during reception This allows for
greater bus latency
When the SONIC-T accesses the Descriptor Areas (i e
RRA RDA CDA and TDA) it transfers data between its
registers and memory All fields which need to be used are
accessed in one block operation Thus the SONIC-T per-
forms 4 accesses in the RRA (see Section 5 4 4 2) 7 ac-
cesses in the RDA (see Section 5 4 6 1) 2 3 or 6 accesses
in the TDA (see Section 5 5 4) and 4 accesses in the CDA
7 3 3 Bus Status
The SONIC-T presents three bits of status information on
pins S2–S0 which indicate the type of bus operation the
SONIC-T is currently performing (Table 7-1) Bus status is
valid when at the falling edge of AS or the rising edge of
ADS
as discussed above
(Continued)
FIGURE 7-4 Bus Request Timing (BMODE
in which the
58
S2
1
1
0
0
0
1
1
0
S1
1
0
0
1
1
1
0
0
S0
1
1
1
1
0
0
0
0
e
TABLE 7-1 Bus Status
1)
The bus is idle The SONIC-T is not
performing any transfers on the bus
The Transmit Descriptor Area (TDA) is
currently being accessed
The Transmit Buffer Area (TBA) is
currently being read
The Receive Buffer Area (RBA) is
currently being written to Only data is
being written though not a Source or
Destination address
The Receive Buffer Area (RBA) is
currently being written to Only the
Source or Destination address is being
written though
The Receive Resource Area (RRA) is
currently being read
The Receive Descriptor Area (RDA) is
currently being accessed
The CAM Descriptor Area (CDA) is
currently being accessed
Status
TL F 11719 – 31