ISP1161ABD ST-Ericsson Inc, ISP1161ABD Datasheet - Page 103

• Manufacturer Part Number: ISP1161ABD
• Description: IC USB HOST/DEVICE CTRLR 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161ABD

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1165; ISP1161ABD,157

Philips Semiconductors
Table 94:
9397 750 13962
Product data
Bit
Symbol
Reset
Access
DcEndpointStatusImage register: bit allocation
EPSTAL
R
7
0
13.2.5 Clear Endpoint Buffer (70H, 72H–7FH)
13.2.6 DcEndpointStatusImage register (D0H–DFH)
EPFULL1
This command unlocks and clears the buffer of the selected OUT endpoint, allowing
the reception of new packets. Reception of a complete packet causes the Buffer Full
flag of an OUT endpoint to be set. Any subsequent packets are refused by returning a
NAK condition, until the buffer is unlocked using this command. For a double-buffered
endpoint this command switches the current FIFO for CPU access.
Remark: For special aspects of the control OUT endpoint see
Code (Hex): 70, 72 to 7F — clear endpoint buffer (control OUT, endpoint 1 to 14)
Transaction — none
This command is used to check the status of the selected endpoint FIFO without
clearing any status or interrupt bits. The command accesses the
DcEndpointStatusImage register, which contains a copy of the DcEndpointStatus
register. The bit allocation of the DcEndpointStatusImage register is shown in
Table
Code (Hex): D0 to DF — check status (control OUT, control IN, endpoint 1 to 14)
Transaction — write/read 1 word
Table 95:
Bit
7
6
5
4
3
2
1
0
R
6
0
94.
DcEndpointStatusImage register: bit description
Symbol
EPSTAL
EPFULL1
EPFULL0
DATA_PID
OVERWRITE
SETUPT
CPUBUF
-
EPFULL0
R
5
0
Rev. 03 — 23 December 2004
DATA_PID
Description
This bit indicates whether the endpoint is stalled or not
(1 = stalled, 0 = not stalled).
Logic 1 indicates that the secondary endpoint buffer is full.
Logic 1 indicates that the primary endpoint buffer is full.
This bit indicates the data PID of the next packet (0 = DATA PID,
1 = DATA1 PID).
This bit is set by hardware, logic 1 indicating that a new Setup
packet has overwritten the previous set-up information, before it
was acknowledged or before the endpoint was stalled. If writing
the set-up data has finished, this bit is cleared by a read action.
Firmware must check this bit before sending an Acknowledge
Setup command or stalling the endpoint. Upon reading logic 1
the firmware must stop ongoing set-up actions and wait for a
new Setup packet.
Logic 1 indicates that the buffer contains a Setup packet.
This bit indicates which buffer is currently selected for CPU
access (0 = primary buffer, 1 = secondary buffer).
reserved
Full-speed USB single-chip host and device controller
R
4
0
WRITE
OVER
R
3
0
SETUPT
R
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
CPUBUF
Section
ISP1161A
R
1
0
11.3.6.
reserved
102 of 134
R
0
0