PCX107AVZFU100LC E2V, PCX107AVZFU100LC Datasheet - Page 27

• Manufacturer Part Number: PCX107AVZFU100LC
• Description: IC PCI BRIDGE MEM CTRLR 503PBGA
• Manufacturer: E2V

Specifications of PCX107AVZFU100LC

• Controller Type: PCI Controller
• Interface: PCI
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 503-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -

7.2.3
Table 7-5.
Notes:
2137D–HIREL–08/05
Num
11a1
11a2
11a3
10a
10b
10c
10d
10e
11b
10f
1. All memory, processor and related interface input signal specifications are measured from the TTL level (0.8 or 2.0V) of the
2. All PCI signals are measured from OV
3. Input timings are measured at the pin.
4. t
5. All mode select input signals specifications are measured from the TTL level (0.8 or 2.0V) of the signal in question to the
Characteristics
PCI Input Signals
Valid to PCI_SYNC_IN (Input Setup)
Memory Interface Signals
Valid to SDRAM_SYNC_IN (Input Setup)
Epic, Misc. Debug Input Signals
Valid to SDRAM_SYNC_IN (Input Setup)
Two-wire interface Input Signals
Valid to SDRAM_SYNC_IN (Input Setup)
Mode select Inputs
Valid to HRESET (Input Setup)
60x Processor Interface Signals
Valid to SDRAM_SYNC_IN (Input Setup)
PCI_SYNC_IN (SDRAM_SYNC_IN) to Inputs Invalid (Input Hold)
Memory Interface Signals
SDRAM_SYNC_IN to Inputs Invalid (Input Hold)
60x Processor Interface Signals
SDRAM_SYNC_IN to Inputs Invalid (Input Hold)
HRESET to Mode select Inputs Invalid (Input Hold)
Input AC Timing Specifications
signal in question to the V
the same as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges
occur on every rising and falling edge of PCI_SYNC_IN). See
PCI signaling levels. See
V
CLK
M
= 1.4V of the rising edge of the HRESET signal. See
Input AC Timing Specifications
is the time of one SDRAM_SYNC_IN clock cycle.
Table 7-5
on page
At recommended operating conditions (see
LV
DD
= 3.3
Figure
M
28.
= 1.4V of the rising edge of the memory bus clock, SDRAM_SYNC_IN. SDRAM_SYNC_IN is
provides the input AC timing specifications. See
±
0.3V
7-6.
DD
/2 of the rising edge of PCI_SYNC_IN to 0.4*OV
Figure 7-7 on page
Figure
Table 5-2 on page
7-5.
9*t
Min
3.0
2.0
2.0
2.0
2.0
1.0
0.5
0
0
28.
CLK
Figure 7-5 on page 28
DD
12) with GV
of the signal in question for 3.3 V
Max
–
–
–
–
–
–
–
–
–
–
DD
Unit
= 3.3V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PC107A
and
Figure 7-6
±
Notes
(1)(3)(5)
(1)(3)(5)
5% and
(2)(3)
(1)(3)
(1)(3)
(1)(3)
(1)(3)
(2)(3)
(1)(3)
(1)(3)
27