PCX107AVZFU100LC E2V, PCX107AVZFU100LC Datasheet - Page 23

• Manufacturer Part Number: PCX107AVZFU100LC
• Description: IC PCI BRIDGE MEM CTRLR 503PBGA
• Manufacturer: E2V

Specifications of PCX107AVZFU100LC

• Controller Type: PCI Controller
• Interface: PCI
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 503-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -

7.2
7.2.1
Table 7-3.
Notes:
2137D–HIREL–08/05
Num
2, 3
1a
1b
5a
5b
9a
9b
9d
10
15
16
17
18
19
20
21
9c
4
7
Dynamic Electrical Characteristics
1. These specifications are for the default driver strengths indicated in
2. Rise and fall times for the PCI_SYNC_IN input are measured from 0.4V to 2.4V.
3. Specification value at maximum frequency of operation.
4. Relock time is guaranteed by design and characterization. Relock time is not tested.
5. Rise and fall times for the OSC_IN input is guaranteed by design and characterization. OSC_IN input rise and fall times are
6. Relock timing is guaranteed by design. PLL-relock time is the maximum amount of time required for PLL lock after a stable
7. DLL_STANDARD is bit 7 of the PMC2 register <72>. N is a non-zero integer (1 or 2). T
8. See
Characteristics and Conditions
Frequency of Operation (PCI_SYNC_IN)
PCI_SYNC_IN Cycle Time
PCI_SYNC_IN Rise and Fall Times
PCI_SYNC_IN Duty Cycle Measured at 1.4V
PCI_SYNC_IN Pulse Width High Measured at 1.4V
PCI_SYNC_IN Pulse Width Low Measured at 1.4V
PCI_SYNC_IN Jitter
PCI_CLK[0–4] Skew (Pin to Pin)
SDRAM_CLK[0–3] Skew (Pin to Pin)
CPU_CLK[0–2] Skew (Pin to Pin)
SDRAM_CLK[0–3]/CPU_CLK[0–2] Jitter
Internal PLL Relock Time
DLL lock range with DLL_STANDARD = 1 (default)
DLL lock range with DLL_STANDARD = 0
Frequency of Operation (OSC_IN)
OSC_IN Cycle Time
OSC_IN Rise and Fall Times
OSC_IN Duty Cycle Measured at 1.4V
OSC_IN Frequency Stability
Clock AC Specifications
not tested.
V
abled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255
bus clocks after the PLL-relock time during the reset sequence.
SDRAM_SYNC_OUT clock cycle in ns. t
runner) from SDRAM_SYNC_OUT to SDRAM_SYNC_IN in ns; 6.25 inches of loop length (unloaded PC board runner) cor-
responds to approximately 1 ns of delay. See
DD
Clock AC Timing Specifications
and PCI_SYNC_IN are reached during the reset sequence. This specification also applies when the PLL has been dis-
Table 8-1 on page 39
Table 7-3
At recommended operating conditions (see
LV
DD
= 3.3
for PCI_SYNC_IN input frequency range for specific PLL_CFG[0–3] settings.
±
provides the clock AC timing specifications as defined in Section.
0.3V
(1)
loop
is the propagation delay of the DLL synchronization feedback loop (PC board
Figure 7-4 on page 25
Table 5-2 on page
Table 7-2 on page
for DLL locking ranges.
See
See
12.5
12.5
Min
80
40
80
40
–
6
6
–
–
–
–
–
–
–
–
Figure 7-3 on page 25
Figure 7-4 on page 25
clk
22.
12) with GV
is the period of one
< 150
Max
500
350
350
150
100
100
2.0
66
15
60
66
15
60
9
9
5
DD
= 3.3V
MHz
MHz
Unit
ppm
ns
ns
ns
ps
ps
ps
ns
ns
ns
ns
ps
ps
µs
ns
PC107A
%
%
±
Notes
(3)(4)(6)
5% and
(8)
(8)
(2)
(3)
(3)
(7)
(7)
(8)
(8)
(5)
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