DS21Q42T Maxim Integrated Products, DS21Q42T Datasheet - Page 65

• Manufacturer Part Number: DS21Q42T
• Description: IC FRAMER ENHANCED T1 4X 128TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q42T

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

HIMR: HDLC INTERRUPT MASK REGISTER (Address = 02 Hex)
RHIR: RECEIVE HDLC INFORMATION REGISTER (Address = 03 Hex)
(MSB)
RABT
(MSB)
RBOC
SYMBOL
SYMBOL
REMPTY
TMEND
RHALF
THALF
RCRCE
ROVR
RBOC
RABT
RVM
RNE
RPE
RPS
TNF
RCRCE
RPE
POSITION
POSITION
HIMR.7
HIMR.6
HIMR.5
HIMR.4
HIMR.3
HIMR.2
HIMR.1
HIMR.0
RHIR.7
RHIR.6
RHIR.5
RHIR.4
RHIR.3
ROVR
RPS
RVM
NAME AND DESCRIPTION
Receive BOC Detector Change of State.
0 = interrupt masked
1 = interrupt enabled
Receive Packet End.
0 = interrupt masked
1 = interrupt enabled
Receive Packet Start.
0 = interrupt masked
1 = interrupt enabled
Receive FIFO Half Full.
0 = interrupt masked
1 = interrupt enabled
Receive FIFO Not Empty.
0 = interrupt masked
1 = interrupt enabled
Transmit FIFO Half Empty.
0 = interrupt masked
1 = interrupt enabled
Transmit FIFO Not Full.
0 = interrupt masked
1 = interrupt enabled
Transmit Message End.
0 = interrupt masked
1 = interrupt enabled
NAME AND DESCRIPTION
Abort Sequence Detected. Set whenever the HDLC controller
sees 7 or more ones in a row.
CRC Error. Set when the CRC checksum is in error.
Overrun. Set when the HDLC controller has attempted to write
a byte into an already full receive FIFO.
Valid Message. Set when the HDLC controller has detected and
checked a complete HDLC packet.
Empty. A real–time bit that is set high when the receive FIFO is
empty.
RHALF
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REMPTY
RNE
POK
THALF
CBYTE
TNF
(LSB)
OBYTE
TMEND
(LSB)