DS21Q42T Maxim Integrated Products, DS21Q42T Datasheet - Page 30

IC FRAMER ENHANCED T1 4X 128TQFP

DS21Q42T

Manufacturer Part Number
DS21Q42T
Description
IC FRAMER ENHANCED T1 4X 128TQFP
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS21Q42T

Controller Type
T1 Framer
Interface
Parallel/Serial
Voltage - Supply
2.97 V ~ 3.63 V
Current - Supply
75mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-TQFP, 128-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS21Q42T
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS21Q42T
Manufacturer:
DALLAS
Quantity:
20 000
Part Number:
DS21Q42T+
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS21Q42TN
Manufacturer:
Maxim Integrated
Quantity:
10 000
TCR2: TRANSMIT CONTROL REGISTER 2 (Address=36 Hex)
Table 6-1. OUTPUT PIN TEST MODES
TEST 1
SYMBOL
(MSB)
TEST1
TD4YM
TZBTSI
TB7ZS
TEST1
TEST0
TSDW
TSIO
TSM
0
0
1
1
TEST0
TEST 0
POSITION
0
1
0
1
TCR2.7
TCR2.6
TCR2.5
TCR2.4
TCR2.3
TCR2.2
TCR2.1
TCR2.0
TZBTSI
Operate normally
Force all of the selected framer’s output pins 3–state (excludes other
Framers I/O pins and parallel port pins)
Force all of the selected framer’s output pins low (excludes other
Framers I/O pins and parallel port pins)
Force all of the selected framer’s output pins high (excludes other framers
I/O pins and parallel port pins)
NAME AND DESCRIPTION
Test Mode Bit 1 for Output Pins. See Table 6–1.
Test Mode Bit 0 for Output Pins. See Table 6–1.
Transmit Side ZBTSI Enable.
0 = ZBTSI disabled
1 = ZBTSI enabled
TSYNC Double–Wide. (note: this bit must be set to zero when
TCR2.3=1 or when TCR2.2=0)
0 = do not pulse double–wide in signaling frames
1 = do pulse double–wide in signaling frames
TSYNC Mode Select.
0 = frame mode (see the timing in Section 20)
1 = multiframe mode (see the timing in Section 20)
TSYNC I/O Select.
0 = TSYNC is an input
1 = TSYNC is an output
Transmit Side D4 Yellow Alarm Select.
0 = zeros in bit 2 of all channels
1 = a one in the S–bit position of frame 12
Transmit Side Bit 7 Zero Suppression Enable.
0 = no stuffing occurs
1 = Bit 7 force to a one in channels with all zeros
TSDW
30 of 116
AFFECT ON OUTPUT PINS
TSM
TSIO
TD4YM
TB7ZS
(LSB)

Related parts for DS21Q42T