COM20022I-HT SMSC, COM20022I-HT Datasheet - Page 43

• Manufacturer Part Number: COM20022I-HT
• Description: IC CTRLR ARCNET 2KX8 RAM 48-TQFP
• Manufacturer: SMSC
• Series: ARCNETr

Specifications of COM20022I-HT

• Controller Type: ARCNET Controller
• Interface: Differential
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 65mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1003

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
SMSC COM20022I
3,2,1
BIT
7
6
5
4
0
Pulse1 Mode
Four NACKS
Reserved
Receive All
Clock Prescaler Bits
3,2,1
Slow Arbitration
Select
BIT NAME
P1MODE
FOUR
NACKS
RCVALL
CKP3,2,1
SLOWARB
SYMBOL
Table 6.10 - Setup 1 Register
DATASHEET
This bit determines the type of PULSE1 output driver used in
Backplane Mode. When high, a push/pull output is used. When
low, an open drain output is used. The default is open drain.
This bit, when set, will cause the EXNACK bit in the Diagnostic
Status Register to set after four NACKs to Free Buffer Enquiry are
detected by the COM20022I. This bit, when reset, will set the
EXNACK bit after 128 NACKs to Free Buffer Enquiry. The default
is 128.
Do not set.
This bit, when set, allows the COM20022I to receive all valid data
packets on the network, regardless of their destination ID. This
mode can be used to implement a network monitor with the
transmitter on- or off-line. Note that ACKs are only sent for
packets received with a destination ID equal to the COM20022I's
programmed node ID. This feature can be used to put the
COM20022I in a 'listen-only' mode, where the transmitter is
disabled and the COM20022I is not passing tokens. Defaults low.
These bits are used to determine the data rate of the COM20022I.
The following table is for a 20 MHz crystal: (Clock Multiplier is
bypassed)
Note: The lowest data rate achievable by the COM20022I is
This bit, when set, will divide the arbitration clock by 2. Memory
cycle times will increase when slow arbitration is selected.
Note: For clock multiplier output clock speeds greater than 40
CKP3
0
0
0
0
1
Page 43
156.25Kbs. Defaults to 000 or 2.5Mbs. For Clock Multiplier
output clock speed greater than 20 MHz, CKP3, CKP2 and
CKP1 must all be zero.
MHz, SLOWARB must be set. Defaults to low.
CKP2
0
0
1
1
0
CKP1
0
1
0
1
0
DESCRIPTION
DIVISOR
128
16
32
64
8
156.25Kbs
312.5Kbs
1.25Mbs
SPEED
625Kbs
2.5Mbs
Revision 09-27-07