COM20022I-HT SMSC, COM20022I-HT Datasheet - Page 22

• Manufacturer Part Number: COM20022I-HT
• Description: IC CTRLR ARCNET 2KX8 RAM 48-TQFP
• Manufacturer: SMSC
• Series: ARCNETr

Specifications of COM20022I-HT

• Controller Type: ARCNET Controller
• Interface: Differential
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 65mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1003

Revision 09-27-07
(Active-High)
(Active-Low)
The timing of the Non-Burst mode DMA data transfer is found in the Timing Diagrams section of this data
sheet. The basic sequence of operation is as follows:
nDACK
DREQ
nDACK becomes active (low) upon DREQ becoming active (high) and catching the host bus (AEN=1).
DREQ becomes inactive after nDACK and read/write signal become active.
DREQ becomes active after nDACK or read/write signal becomes inactive.
DREQ becomes inactive after TC and the read/write signal assert (when nDACK=0). In this case,
DREQ doesn't become active again after nDACK becomes inactive.
nDACK becomes inactive after DREQ=0 and the present cycle finishes.
Figure 5.4 -
Programmable Burst Mode DMA Transfer (Rough Timing)
(Counting Read/Write pulse
or counting internal timer)
DATASHEET
Transfer term
Page 22
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Gate
Time
Transfer
SMSC COM20022I
Restart
Datasheet