COM20022I-HT SMSC, COM20022I-HT Datasheet - Page 40

• Manufacturer Part Number: COM20022I-HT
• Description: IC CTRLR ARCNET 2KX8 RAM 48-TQFP
• Manufacturer: SMSC
• Series: ARCNETr

Specifications of COM20022I-HT

• Controller Type: ARCNET Controller
• Interface: Differential
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 65mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1003

Revision 09-27-07
BIT
5-4
2-0
7
6
3
Read Data
Auto Increment
(Reserved)
DMA Enable
Address 10-8
BIT NAME
RDDATA
AUTOINC
DMAEN
A10-A8
SYMBOL
Table 6.6 - Address Pointer High Register
DATASHEET
These bits are undefined.
This bit tells the COM20022I whether the following access will be
a read or write. A logic "1" prepares the device for a read, a logic
"0" prepares it for a write.
This bit controls whether the address pointer will increment
automatically. A logic "1" on this bit allows automatic increment of
the pointer after each access, while a logic "0" disables this
function. Please refer to the Sequential Access Memory section
for further detail.
This bit is used to Disable/Enable the assertion of the DMA
Request (DREQ pin) after writing the Address Pointer Low
register. DMAEN=0: Disable (Default). DMAEN=1: Enable the
assertion of the DREQ pin after writing the Address Pointer Low
register. Writing DMAEN=0 during the DMA operation will negate
the DREQ pin immediately. The DMA operation is terminated
immediately after the next DACK pin negation. The inverting
signal of DAMEN is the Interrupt source signal DMAEND. The
DMAEN bit is cleared automatically by finishing the DMA. If the
DMAEND bit in the Mask register is not masked, the Interrupt
occurs by finishing the DMA operation.
These bits hold the upper three address bits which provide
addresses to RAM.
Page 40
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
DESCRIPTION
SMSC COM20022I
Datasheet