IDT82V2108PXG IDT, Integrated Device Technology Inc, IDT82V2108PXG Datasheet - Page 273
IDT82V2108PXG
Manufacturer Part Number
IDT82V2108PXG
Description
IC FRAMER T1/J1/E1 8CH 128-PQFP
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT82V2108PX8.pdf
(292 pages)
Specifications of IDT82V2108PXG
Controller Type
T1/E1/J1 Framer
Interface
Parallel
Voltage - Supply
2.97 V ~ 3.63 V
Current - Supply
160mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
128-MQFP, 128-PQFP
Screening Level
Industrial
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82V2108PXG
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Company:
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Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
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IDT82V2108
T1 / J1 PRGD Pattern Detector #1 (06CH)
T1 / J1 PRGD Pattern Detector #2 (06DH)
T1 / J1 PRGD Pattern Detector #3 (06EH)
T1 / J1 PRGD Pattern Detector #4 (06FH)
ters. They reflect the content of the received pattern.
value in these registers represents the number of bit errors. The bit errors are not accumulated when the pattern is out of synchronization.
value in these registers represents the total received bit number.
register.
Programming Information
Bit Name
Bit Name
Bit Name
Bit Name
Default
Default
Default
Default
Bit No.
Bit No.
Bit No.
Bit No.
Type
Type
Type
Type
When the PDR[1:0] (b7~6, T1/J1-060H) are set to ‘00’ or ‘01’, the four PRGD pattern detector registers are configured as Pattern Receive regis-
When the PDR[1:0] (b7~6, T1/J1-060H) are set to ‘10’, the four PRGD pattern detector registers are configured as Error Counter registers. The
When the PDR[1:0] (b7~6, T1/J1-060H) are set to ‘11’, the four PRGD pattern detector registers are configured as Bit Counter registers. The
These registers are updated each second automatically, or by writing to any of these four registers, or to the Revision / Chip ID / Global PMON
PD[15]
PD[23]
PD[31]
PD[7]
R
X
R
X
R
X
R
X
7
7
7
7
PD[14]
PD[22]
PD[30]
PD[6]
R
R
R
R
6
X
6
X
6
X
6
X
PD[13]
PD[21]
PD[29]
PD[5]
R
X
R
X
R
X
R
X
5
5
5
5
PD[12]
PD[20]
PD[28]
PD[4]
R
X
R
X
R
X
R
X
4
4
4
4
263
PD[19]
PD[27]
PD[11]
PD[3]
R
X
R
X
R
X
R
X
3
3
3
3
PD[18]
PD[26]
PD[10]
PD[2]
R
R
R
R
2
X
2
X
2
X
2
X
T1 / E1 / J1 OCTAL FRAMER
PD[17]
PD[25]
PD[1]
PD[9]
R
X
R
X
R
X
R
X
1
1
1
1
March 5, 2009
PD[16]
PD[24]
PD[0]
PD[8]
R
X
R
X
R
X
R
X
0
0
0
0
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