IDT82V2108BB IDT, Integrated Device Technology Inc, IDT82V2108BB Datasheet - Page 22

• Manufacturer Part Number: IDT82V2108BB
• Description: IC FRAMER T1/J1/E1 8CH 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108BB

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-BGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108BB

IDT82V2108
3
3.1
framer, or a duplex eight ports T1 framer, or a duplex eight ports J1
framer. When the TMODE (b0, 400H)
mode. When the TMODE (b0, 400H) is set to ‘1’, the device is in T1/J1
mode (default mode). In T1/J1 mode, when the JYEL (b3, T1/J1-020H)
and the J1_YEL (b5, T1/J1-02CH) are both set to ‘0’, the receive path of
the corresponding framer is in T1 mode; when the JYEL (b3, T1/J1-
020H) and the J1_YEL (b5, T1/J1-02CH) are both set to ‘1’, the receive
path of the corresponding framer is in J1 mode; when the J1_CRC (b6,
T1/J1-044H) and the J1_YEL (b5, T1/J1-044H) are both set to ‘0’, the
transmit path of the corresponding framer is in T1 mode; when the
J1_CRC (b6, T1/J1-044H) and the J1_YEL (b5, T1/J1-044H) are both
set to ‘1’, the transmit path of the corresponding framer is in J1 mode.
1. The contents in the brackets indicate the position of this bit and the address of the regis-
ter. If more than one register contains the same bit, the address is only for the first register,
the addresses of the remaining registers are listed together with the first register in the
Register Description paragraph.
Functional Description
Note:
The IDT82V2108 can be configured as a duplex eight ports E1
FUNCTIONAL DESCRIPTION
T1 / E1 / J1 MODE SELECTION
1
is set to ‘0’, the device is in E1
12
3.2
3.2.1
chronization, CRC Multi-Frame synchronization, and Channel Associ-
ated Signaling (CAS) Multi-Frame synchronization in the received data
stream. Figure 3 shows the searching process.
monitoring the received data stream. The Frame Processor will indicate
framing bit errors, CAS Multi-Frame alignment pattern errors, CRC
Multi-Frame alignment pattern errors or CRC errors, if any. The status of
loss of frame, loss of Signaling Multi-Frame and loss of CRC Multi-
Frame can also be detected and declared based on user-selectable cri-
teria. The reframe operation can be initiated by excessive CRC errors,
or the CRC Multi-Frame alignment is not found within 400ms. A software
reset will also make the Frame Processor reframe.
output the extracted data on a separate pin. The Frame Processor also
extracts the contents of the International bits (from both the FAS and the
NFAS frames), the National bits and the Extra bits (from TS16 in the
frame 0 of the Signaling Multi-Frame), and stores these data in registers.
The CRC Sub Multi-Frame alignment 4-bit codeword in the National bit
positions Sa4 to Sa8 can also be extracted and stored in registers, and
updated every CRC Sub Multi-Frame.
of NFAS frames) and Remote Signaling Multi-Frame Alarm (bit 6 of
TS16 of frame 0 of Signaling Multi-Frame). The “de-bounced” Remote
Alarm and Remote Signaling Multi-Frame Alarm can be indicated if the
corresponding bit has been a certain logic for consecutive 2 or 3 times.
The AIS (Alarm Indication Signal) can also be detected, and if the AIS
condition has persisted for at least 100 ms, an AIS Alarm is declared.
The Frame Processor can also declare a Red Alarm if the out-of-frame
condition has persisted for at least 100 ms.
occurrence of some events. The interrupts may be generated every
Basic Frame, CRC Sub Multi-Frame, CRC Multi-Frame or Signaling
Multi-Frame.
data.
The Frame Processor of each framer operates independently.
In E1 mode, the Frame Processor searches for Basic Frame syn-
Once the frame is synchronized, the Frame Processor keeps on
The Frame Processor can extract the data stream in TS16, and
The Framer Processor identifies the Remote Alarm bit (bit 3 of TS0
An interrupt output is provided to indicate status changes and the
The Frame Processor can also be bypassed to receive unframed
FRAME PROCESSOR (FRMP)
E1 MODE
T1 / E1 / J1 OCTAL FRAMER
March 5, 2009