IDT82V2108BB IDT, Integrated Device Technology Inc, IDT82V2108BB Datasheet - Page 163
IDT82V2108BB
Manufacturer Part Number
IDT82V2108BB
Description
IC FRAMER T1/J1/E1 8CH 144-BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT82V2108PX8.pdf
(292 pages)
Specifications of IDT82V2108BB
Controller Type
T1/E1/J1 Framer
Interface
Parallel
Voltage - Supply
2.97 V ~ 3.63 V
Current - Supply
160mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
144-BGA
Screening Level
Industrial
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
82V2108BB
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IDT82V2108
E1 TJAT Configuration (027H, 0A7H, 127H, 1A7H, 227H, 2A7H, 327H, 3A7H)
CENT:
UNDE:
OVRE:
LIMIT:
the read pointer is 1 UI away from the FIFO being empty or full. This limitation of jitter attenuation ensures that no data is lost during high phase shift
conditions.
Programming Information
Bit Name
Default
Bit No.
Type
The CENT allows the TJAT FIFO to self-center its read pointer, maintaining the pointer at least 4 UI away from the FIFO being empty or full.
= 0: Disable the self-center. Data is pass through uncorrupted.
= 1: Enable the FIFO to self-center its read pointer when the FIFO is 4 UI away from being empty or full.
A positive transition on this bit will execute a self-center action immediately.
This bit decides whether to generate an interrupt when the TJAT FIFO is under-run.
= 0: No interrupt is generated when the TJAT FIFO is under-run.
= 1: An interrupt on the INT pin is generated when the TJAT FIFO is under-run.
This bit decides whether to generate an interrupt when the TJAT FIFO is overwritten.
= 0: No interrupt is generated when the TJAT FIFO is overwritten.
= 1: An interrupt on the INT pin is generated when the TJAT FIFO is overwritten.
= 0: Disable the limitation of the jitter attenuation.
= 1: Enable the DPLL to limit the jitter attenuation by enabling the FIFO to increase or decrease the frequency of the output smoothed clock when
7
Reserved
6
5
CENT
R/W
4
0
153
UNDE
R/W
3
0
OVRE
R/W
2
0
T1 / E1 / J1 OCTAL FRAMER
Reserved
1
March 5, 2009
LIMIT
R/W
0
1
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