Z16C3510VSG Zilog, Z16C3510VSG Datasheet - Page 57

• Manufacturer Part Number: Z16C3510VSG
• Description: IC 10MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3510VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM011001-0601
The /DTR//REQ pin carries inverted state of the DTR bit
(D7) in WR5 unless this pin has been programmed to carry
a DMA Request signal.
The /DCD pin is ordinarily a simple input to the DCD bit in
RR0. However, if the Auto Enables mode is selected by
setting bit D5 of WR3 to “1”, this pin becomes an enable
for the receiver. That is, if Auto Enable is on and the /DCD
pin is High the receiver is disabled. While the /DCD pin is
Low, the receiver is enabled.
The initialization sequence for the receiver in SDLC mode
is WR4 first, to select the mode, then WR10 to modify it if
necessary, WR6 to program the address, WR7 to program
the flag and WR3 and WR5 to select the various options.
At this point the other registers should be initialized as nec-
essary. When all of this is completed the receiver may be
enabled by setting bit 0 of WR3 to a one. A summary is
shown in Table 4-13.
Notes:
4.4.3 SDLC LOOP MODE
The ISCC supports SDLC Loop mode in addition to normal
SDLC. SDLC Loop mode is very similar to normal SDLC
but is usually used in applications where a point-to-point
network is not appropriate (for example, Point-of-Sale ter-
minals). In an SDLC Loop there is a primary controller that
manages the message traffic flow on the loop and any
number of secondary stations. In SDLC Loop mode, the
ISCC operating in regular SDLC mode can act as the pri-
mary controller.
Table 4-13. Initializing the Receiver in SDLC Mode
Register
WR3
WR4
WR5
WR10
WR5
WR6
WR7
WR3
The receiver searches for synchronization when it is in Hunt
mode. In this mode the receiver is idle except that it is search-
ing the data stream for a flag match.
When the receiver detects a flag match it achieves synchroni-
zation and interprets the following byte as the address field.
The SYNC/HUNT bit in RR0 reports the Hunt Status and an in-
terrupt can be generated upon transitions between the Hunt
state and the Sync state.
The ISCC will drive the /SYNC pin Low to signal that the flag
has been received.
Bit No
6-7
0-1
5-6
0-7
0-7
2
7
7
5
Description
Number of bits per character
Select parity
Select CRC-CCITT Generator
Select CRC preset value
Select NRZ/NRZI encoding
DTR/REQ
Address
Flag
Auto enable
A secondary station in an SDLC Loop is always listening
to the messages being sent around the loop, and in fact
must pass these messages to the rest of the loop by re-
transmitting them with a one-bit-time delay.
The secondary station can place its own message on the
loop only at specific times. The controller signals that sec-
ondary stations may transmit messages by sending a spe-
cial character, called an EOP (End of Poll), around the
loop. The EOP character is the bit pattern 11111110.
When a secondary station has a message to transmit and
recognizes an EOP on the line, it changes the last binary
1 of the EOP to a 0 before transmission. This has the effect
of turning the EOP into a flag pattern. The secondary sta-
tion now places its message on the loop and terminates its
message with an EOP. Any secondary stations further
down the loop with messages to transmit can append their
messages to the message of the first secondary station by
the same process.
All secondary stations without messages to send merely
echo the incoming messages and are prohibited from plac-
ing messages on the loop, except upon recognizing an
EOP.
SDLC Loop mode is quite similar to normal SDLC mode
except that two additional control bits are used. Writing a 1
to the Loop Mode bit in WR10 configures the ISCC for
Loop mode. Writing a 1 to the Go Active on Poll bit in the
same register normally causes the ISCC to change the
next EOP into a flag and then begin transmitting on loop.
However, when the ISCC first goes on loop it uses the first
EOP as a signal to insert the one-bit delay, and doesn’t be-
gin transmitting until it receives the second EOP. There are
also two additional status bits in RR10, the On Loop bit and
the Loop Sending bit.
There are also restrictions as to when and how a second-
ary station physically becomes part of the loop.
A secondary station that has just powered up must monitor
the loop, without the one-bit-time delay, until it recognizes
an EOP. When an EOP is recognized the one-bit-time de-
lay is switched on. This does not disturb the loop because
the line is marking idle between the time that the controller
sends the EOP and the time that it receives the EOP back.
The secondary station that has gone on-loop cannot place
a message on the loop until the next time that an EOP is
issued by the controller. A secondary station goes off-loop
in a similar manner. When given a command to go off-loop,
the secondary station waits until the next EOP to remove
the one-bit-time delay.
To operate the ISCC in SDLC Loop mode, the ISCC must
first be programmed just as if normal SDLC were to be
used. Loop mode is then selected by writing the appropri-
ate control word in WR10; the ISCC is now waiting for the
Z16C35ISCC™ User’s Manual
Data Communication Modes
4-23
4