Z16C3510VSG Zilog, Z16C3510VSG Datasheet - Page 3

• Manufacturer Part Number: Z16C3510VSG
• Description: IC 10MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3510VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM011001-0601
1.1 INTRODUCTION
The Z16C35, ISCC
with a flexible Bus Interface Unit (BIU) connecting a built-
in Direct Memory Access (DMA) cell to the CMOS Serial
Communications Control (SCC) cell.
The ISCC is a dual-channel, multi-protocol data communi-
cations peripheral which easily interfaces to CPU’s with ei-
ther multiplexed or non-multiplexed address and data bus-
es. The advanced CMOS process offers lower power
consumption, higher performance, and superior noise im-
munity. The programming flexibility of the internal registers
allow the ISCC to be configured for a wide variety of serial
communications applications. The many on-chip features
such as streamlined bus interface, four channel DMA,
baud rate generators, digital phase-locked loops, and crys-
tal oscillators dramatically reduce the need for external log-
ic. Additional features, including a 10x19 bit status FIFO,
are added to support high speed SDLC transfers using on-
chip DMA controllers.
The ISCC can address up to 4 gigabytes per DMA channel
by using the /UAS and /AS signals to strobe out 32-bit mul-
tiplexed addresses.
The ISCC handles asynchronous formats, synchronous
byte-oriented protocols such as IBM Bisync, and synchro-
nous bit-oriented protocols such as HDLC and IBM SDLC.
This versatile device supports virtually any serial data
transfer application (terminals, printers, diskette, tape
drives, etc.).
™
is a CMOS superintegration device
U
C
G
The device can generate and check CRC codes in any
synchronous mode and can be programmed to check data
integrity in various modes. The ISCC also has facilities for
modem controls in both channels. In applications where
these controls are not needed, the modem controls can be
used for general-purpose I/O.
The standard Zilog interrupt daisy chain is supported for in-
terrupt hierarchy control. Internally, the SCC cell has high-
er interrupt priority than the DMA cell.
The DMA cell consists of four DMA channels; one for trans-
mit and one for receive to and from each SCC channel, re-
spectively.
The DMA cell adopts a simple fly-by-mode DMA transfer,
providing a powerful and efficient DMA access. The cell
does not support memory-to-memory transfer.
Priorities between the four DMA channels are programma-
ble to custom-fit user applications. Arbitration of Bus prior-
ity control signals between the ISCC DMA and other sys-
tem DMA’s should be handled outside the ISCC.
The BIU has a universal interface to most system/CPU bus
structures and timing. The first write to the ISCC after a
hardware reset will configure the bus interface type being
implemented.
SER
ENERAL
HAPTER
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S
M
ANUAL
D
ESCRIPTION
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