TDA8023TT/C1,118 NXP Semiconductors, TDA8023TT/C1,118 Datasheet - Page 8

• Manufacturer Part Number: TDA8023TT/C1,118
• Description: IC SMART CARD INTERFACE 28-TSSOP
• Manufacturer: NXP Semiconductors

Specifications of TDA8023TT/C1,118

• Package / Case: 28-TSSOP
• Controller Type: Smart Card Interface
• Interface: I²C
• Voltage - Supply: 2.7 V ~ 6.5 V
• Current - Supply: 200mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935274975118; TDA8023TT-T; TDA8023TT-T

NXP Semiconductors
TDA8023_1
Product data sheet
8.2.4 Shutdown mode
8.3.1 I
8.3.2 Bus conditions
8.3.3 Data transfer
8.3 I
When pin SDWN = HIGH, the TDA8023 is in Shutdown mode; the consumption in this
mode is less than 10 A. The I
If the card is extracted or inserted when the TDA8023 is in Power-down mode, pin INT
becomes LOW and stays LOW as long as pin SDWN = HIGH.
When pin SDWN is pulled LOW, the TDA8023 leaves Shutdown mode and executes a
complete power-on reset sequence.
A 400 kHz I
status.
The I
consists of two bidirectional lines: one for data signals (SDA) and one for clock signals
(SCL).
Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up
resistor.
The following protocol has been defined:
The following bus conditions have been defined.
Bus not busy — Both data and clock lines remain HIGH.
Start data transfer — A change in the state of the data line from HIGH to LOW, while the
clock is HIGH, defines the START condition.
Stop data transfer — A change in the state of the data line from LOW to HIGH, while the
clock is HIGH, defines the STOP condition.
Data valid — The state of the data line represents valid data when, after a START
condition, the data line is stable for the duration of the HIGH period of the clock signal.
There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP
condition (see
Data transfer is unlimited in the Read mode. The information is transmitted in bytes and
each receiver acknowledges with a 9th bit.
2
2
•
•
C-bus protocol
C-bus
Data transfer may be initiated only when the bus is not busy
During data transfer, the data line must remain stable whenever the clock line is
HIGH; changes in the data line while the clock line is HIGH will be interpreted as
control signals
2
C-bus is for 2-way 2-line communication between ICs or modules. The serial bus
2
C-bus slave interface is used for configuring the TDA8023 and reading the
Figure
7). See
Rev. 01 — 16 July 2007
Table 15
2
C-bus is unresponsive.
for timing information.
Low power IC card interface
TDA8023
© NXP B.V. 2007. All rights reserved.
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