DS21Q43AT Maxim Integrated Products, DS21Q43AT Datasheet - Page 22

• Manufacturer Part Number: DS21Q43AT
• Description: IC FRAMER E1 QUAD 5V IND 128TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q43AT

• Controller Type: E1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 32mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Dc: 0319
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

This means that if an event occurs and a bit is set to a 1 in any of the registers, it will remain set until the
user reads that bit. The bit will be cleared when it is read and it will not be set again until the event has
occurred again or if the alarm is still present.
The user will always precede a read of the SR1, SR2, and RIR registers with a write. The byte written to
the register will inform the DS21Q43A which bits the user wishes to read and have cleared. The user will
write a byte to one of these three registers, with a 1 in the bit positions he or she wishes to read and a 0 in
the bit positions he or she does not wish to obtain the latest information. When a 1 is written to a bit
location, the read register will be updated with current value and it will be cleared. When a 0 is written to
a bit position, the read register will not be updated and the previous value will be held. A write to the
status and information registers will be immediately followed by a read of the same register. The read
result should be logically AND’ed with the mask byte that was just written and this value should be
written back into the same register to insure that bit does indeed clear. This second write step is necessary
because the alarms and events in the status registers occur asynchronously in respect to their access via
the parallel port. This write-read-write scheme allows an external microcontroller or microprocessor to
individually poll certain bits without disturbing the other bits in the register. This operation is key in
controlling the DS21Q43A with higher-order software languages.
status of the synchronizer in real time. This register is not latched and it is not necessary to precede a read
of this register with a write.
The SR1 and SR2 registers have the unique ability to initiate a hardware interrupt via the
four of the framers share the
masked or unmasked from the interrupt pins via the Interrupt Mask Register 1 (IMR1) and Interrupt Mask
Register 2 (IMR2) respectively. The user can determine which framer has active interrupts by polling the
Interrupt Status Register (ISR).
ISR: INTERRUPT STATUS REGISTER (see Table 1-6, Note 2)
The SSR register operates differently than the other three. It is a read only register and it reports the
(MSB)
F3SR2
SYMBOL
F3SR2
F3SR1
F2SR2
F2SR1
F1SR2
F1SR1
F0SR2
F0SR1
F3SR1
POSITION
ISR.7
ISR.6
ISR.5
ISR.4
ISR.3
ISR.2
ISR.1
ISR.0
F2SR2
INT
output. Each of the alarms and events in the SR1 and SR2 can be either
NAME AND DESCRIPTION
Status of Interrupt for SR2 in Framer 3. 1=interrupt active.
Status of Interrupt for SR1 in Framer 3. 1=interrupt active.
Status of Interrupt for SR2 in Framer 2. 1=interrupt active.
Status of Interrupt for SR1 in Framer 2. 1=interrupt active.
Status of Interrupt for SR2 in Framer 1. 1=interrupt active.
Status of Interrupt for SR1 in Framer 1. 1=interrupt active.
Status of Interrupt for SR2 in Framer 0. 1=interrupt active.
Status of Interrupt for SR1 in Framer 0. 1=interrupt active.
F2SR1
22 of 60
F1SR2
F1SR1
F0SR2
INT
F0SR1
DS21Q43A
(LSB)
pin. All