LAN9211-ABZJ SMSC, LAN9211-ABZJ Datasheet - Page 38

• Manufacturer Part Number: LAN9211-ABZJ
• Description: IC ETHERNET CTLR SGL CHIP 56-QFN
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9211-ABZJ

• Controller Type: Ethernet Controller
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3.3 V
• Supply Current (max): 86 mA
• Maximum Operating Temperature: + 70 C
• Ethernet Connection Type: 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• No. Of Ports: 2
• Ethernet Type: IEEE 802.3 / 802.3u
• Interface Type: HBI
• Supply Current: 86mA
• Supply Voltage Range: 2.97V To 3.63V
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1049-6

Revision 2.7 (03-15-10)
3.9.2.1
If an operation is attempted, and an EEPROM device does not respond within 30mS, the LAN9211
will timeout, and the EPC timeout bit (EPC_TO) in the E2P_CMD register will be set.
Figure 3.4, "EEPROM Access Flow Diagram"
EEPROM Read or Write operation.
The host can disable the EEPROM interface through the GPIO_CFG register. When the interface is
disabled, the EEDIO and ECLK signals can be used as general-purpose outputs, or they may be used
to monitor internal MII signals.
Supported EEPROM Operations
The EEPROM controller supports the following EEPROM operations under host control via the
E2P_CMD register. The operations are commonly supported by “93C46” EEPROM devices. A
description and functional timing diagram is provided below for each operation. Please refer to the
E2P_CMD register description in
page 101
Busy Bit = 0
for E2P_CMD field settings for each command.
EEPROM Write
Figure 3.4 EEPROM Access Flow Diagram
Write Data
Command
Command
Register
Register
Register
Write
Read
Idle
DATASHEET
Section 5.3.23, "E2P_CMD – EEPROM Command Register," on
High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
38
illustrates the host accesses required to perform an
EEPROM Read
Read Data
Command
Command
Register
Register
Register
Write
Read
Idle
Busy Bit = 0
SMSC LAN9211
Datasheet