LAN9211-ABZJ SMSC, LAN9211-ABZJ Datasheet - Page 133

IC ETHERNET CTLR SGL CHIP 56-QFN

LAN9211-ABZJ

Manufacturer Part Number
LAN9211-ABZJ
Description
IC ETHERNET CTLR SGL CHIP 56-QFN
Manufacturer
SMSC
Type
Single Chip MAC and PHY Controllerr
Datasheet

Specifications of LAN9211-ABZJ

Controller Type
Ethernet Controller
Interface
Serial EEPROM
Voltage - Supply
3.3V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-QFN
Product
Ethernet Controllers
Number Of Transceivers
1
Standard Supported
IEEE 802.3 or IEEE 802.3u
Data Rate
10 Mbps or 100 Mbps
Supply Voltage (max)
5 V
Supply Voltage (min)
3.3 V
Supply Current (max)
86 mA
Maximum Operating Temperature
+ 70 C
Ethernet Connection Type
100BASE-TX or 10BASE-T
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
No. Of Ports
2
Ethernet Type
IEEE 802.3 / 802.3u
Interface Type
HBI
Supply Current
86mA
Supply Voltage Range
2.97V To 3.63V
Operating Temperature Range
0°C To +70°C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
638-1049-6

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LAN9211-ABZJ
Manufacturer:
Standard
Quantity:
3
Part Number:
LAN9211-ABZJ
Manufacturer:
SMSC
Quantity:
1 154
Part Number:
LAN9211-ABZJ
Manufacturer:
SMSC
Quantity:
20 000
High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
Datasheet
SMSC LAN9211
6.6
SYMBOL
t
cycle
t
t
t
t
t
t
csh
asu
dsu
csl
ah
dh
nCS, nWR
Data Bus
A[7:1]
PIO writes are used for all LAN9211 write cycles. PIO writes can be performed using Chip Select (nCS)
or Write Enable (nWR). Either or both of these control signals must go high between cycles for the
period specified.
Note: The “Data Bus” width is 16 bits.
Note: A PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when either
PIO Writes
DESCRIPTION
Write Cycle Time
nCS, nWR Deassertion Time
Address Setup to nCS, nWR Assertion
Address Hold Time
Data Setup to nCS, nWR Deassertion
Data Hold Time
nCS, nWR Assertion Time
or both nCS and nWR are deasserted. They may be asserted and deasserted in any order.
Figure 6.5 PIO Write Cycle Timing
Table 6.7 PIO Write Cycle Timing
DATASHEET
133
MIN
45
32
13
0
7
0
0
TYP
MAX
Revision 2.7 (03-15-10)
UNITS
ns
ns
ns
ns
ns
ns
ns

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