ISP1362BDFA ST-Ericsson Inc, ISP1362BDFA Datasheet - Page 21

• Manufacturer Part Number: ISP1362BDFA
• Description: IC USB OTG CONTROLLER 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1362BDFA

• Controller Type: USB 2.0 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 568-1219; ISP1362BD,151; ISP1362BD-S

NXP Semiconductors
ISP1362_5
Product data sheet
8.4 PIO access to internal control registers
Table 5
decoding must combine with the chip select signal (CS) and address lines (A1 and A0).
The direction of access of I/O ports, however, is controlled by the RD and WR signals.
When RD is LOW, the microprocessor reads data from the data port of the ISP1362 (see
Figure
or writes data to the data port (see
Table 5.
The register structure in the ISP1362 is a command-data register pair structure. A
complete register access needs a command phase followed by a data phase. The
command (also named as the index of a register) is used to inform the ISP1362 about the
register that will be accessed at the data phase.
On the 16-bit data bus of a microprocessor, a command occupies the lower byte and the
upper byte is filled with zeros (see
For 32-bit registers, the access cycle is shown in
phase followed by two data phases.
CS
L
L
L
L
Fig 10. Microprocessor access to the Host Controller or the Peripheral Controller
10). When WR is LOW, the microprocessor writes command to the command port
shows the I/O port addressing in the ISP1362. The complete I/O port address
When A1 = L, the microprocessor accesses the Host Controller.
When A1 = H, the microprocessor accesses the Peripheral Controller.
A1
L
L
H
H
I/O port addressing
A0
L
H
L
H
Rev. 05 — 8 May 2007
Access
R/W
W
R/W
W
microprocessor
bus interface
A1
Figure
Figure
Data bus width
16 bits
16 bits
16 bits
16 bits
Bus interface
12).
11).
0
1
Device bus interface
Host bus interface
Figure
004aaa122
Description
Host Controller data port
Host Controller command port
Peripheral Controller data port
Peripheral Controller command port
Single-chip USB OTG Controller
13. It consists of a command
© NXP B.V. 2007. All rights reserved.
ISP1362
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