ISP1362BDFA ST-Ericsson Inc, ISP1362BDFA Datasheet - Page 119

• Manufacturer Part Number: ISP1362BDFA
• Description: IC USB OTG CONTROLLER 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1362BDFA

• Controller Type: USB 2.0 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 568-1219; ISP1362BD,151; ISP1362BD-S

NXP Semiconductors
Table 127. DcEndpointStatusImage register: bit allocation
ISP1362_5
Product data sheet
Bit
Symbol
Reset
Access
15.2.6 DcEndpointStatusImage register (D0h to DFh)
15.2.7 Acknowledge set up (F4h)
EPSTAL
R
7
0
Code (Hex): 70, 72 to 7F — clear endpoint buffer (control OUT, endpoints 1 to 14)
Transaction — none (code only)
This command is used to check the status of the selected endpoint buffer memory, without
clearing any status or interrupt bits. The command accesses the DcEndpointStatusImage
register, which contains a copy of the DcEndpointStatus register. The bit allocation of the
DcEndpointStatusImage register is shown in
Code (Hex): D0 to DF — check status (control OUT, control IN, endpoints 1 to 14)
Transaction — write or read 1 byte (code or data)
Table 128. DcEndpointStatusImage register: bit description
This command acknowledges to the host that a set-up packet is received. The arrival of a
set-up packet disables the Validate Buffer and Clear Buffer commands for the control IN
and OUT endpoints. The microprocessor must re-enable these commands by sending an
acknowledge set-up command, see
Code (Hex): F4 — acknowledge set up
Transaction — none (code only)
Bit
7
6
5
4
3
2
1
0
EPFULL1
Symbol
EPSTAL
EPFULL1
EPFULL0
DATA_PID
OVERWRITE
SETUPT
CPUBUF
-
R
6
0
EPFULL0
R
5
0
Description
This bit indicates whether the endpoint is stalled or not (1 = stalled; 0 =
not stalled).
Logic 1 indicates that the secondary endpoint buffer is full.
Logic 1 indicates that the primary endpoint buffer is full.
This bit indicates data PID of the next packet (0 = DATA0 PID; 1 =
DATA1 PID).
This bit is set by hardware. Logic 1 indicates that a new set-up packet
has overwritten the previous set-up information, before it was
acknowledged or before the endpoint was stalled. Once writing of the
set-up data is completed, a read back of this register clears this bit.
Firmware must check this bit before sending an acknowledge set-up
command or stalling the endpoint. On reading logic 1, firmware must
stop ongoing set-up actions and wait for a new set-up packet.
Logic 1 indicates that the buffer contains a set-up packet.
This bit indicates which buffer is currently selected for CPU access (0 =
primary buffer; 1 = secondary buffer).
reserved
Rev. 05 — 8 May 2007
DATA_PID
R
4
0
Section
WRITE
OVER
12.3.6.
R
Table
3
0
127.
SETUPT
Single-chip USB OTG Controller
R
2
0
CPUBUF
R
1
0
© NXP B.V. 2007. All rights reserved.
ISP1362
reserved
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