ISP1362BDFA ST-Ericsson Inc, ISP1362BDFA Datasheet - Page 123

IC USB OTG CONTROLLER 64-LQFP

ISP1362BDFA

Manufacturer Part Number
ISP1362BDFA
Description
IC USB OTG CONTROLLER 64-LQFP
Manufacturer
ST-Ericsson Inc
Datasheet

Specifications of ISP1362BDFA

Controller Type
USB 2.0 Controller
Interface
Parallel/Serial
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Other names
568-1219
ISP1362BD,151
ISP1362BD-S

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISP1362BDFA
Manufacturer:
STE
Quantity:
5
Part Number:
ISP1362BDFA
Manufacturer:
ST-Ericsson Inc
Quantity:
10 000
NXP Semiconductors
Table 139. DcChipID register: bit allocation
Table 141. DcInterrupt register: bit allocation
ISP1362_5
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
BUSTATUS
15.3.6 DcInterrupt register (R: C0h)
EP14
EP6
15
31
23
15
R
R
R
R
R
0
7
0
0
0
7
0
-
-
Table 140. DcChipID register: bit description
This command indicates the sources of interrupts as stored in the 4 bytes DcInterrupt
register. Each individual endpoint has its own interrupt bit. The bit allocation of the
DcInterrupt register is shown in
status in the interrupt service routine. Interrupts are enabled using the DcInterruptEnable
register, see
While reading the DcInterrupt register, it is recommended that both 2 bytes words are
read completely.
Code (Hex): C0 — read DcInterrupt register
Transaction — read 4 bytes (code or data)
Bit
15 to 8
7 to 0
SP_EOT
EP13
EP5
14
30
22
14
R
R
R
R
R
0
6
0
0
0
6
0
-
-
Symbol
CHIPIDH[7:0]
CHIPIDL[7:0]
Section
PSOF
EP12
EP4
13
29
21
13
R
R
R
R
R
1
5
1
0
0
5
0
-
-
15.1.5.
Rev. 05 — 8 May 2007
Description
chip ID code (36h)
silicon version (30h, with 30 representing the BCD encoded version
number)
EP11
SOF
EP3
Table
12
28
20
12
R
R
R
R
R
1
4
1
0
0
4
0
-
-
CHIPIDH[7:0]
CHIPIDL[7:0]
reserved
141. Bit BUSTATUS is used to verify the current bus
EP10
EOT
EP2
11
27
19
11
R
R
R
R
R
0
3
0
0
0
3
0
-
-
SUSPND
Single-chip USB OTG Controller
EP9
EP1
10
26
18
10
R
R
R
R
R
1
2
0
0
0
2
0
-
-
RESUME
EP0IN
EP8
25
17
R
R
R
R
R
9
1
1
0
0
9
0
1
0
-
-
© NXP B.V. 2007. All rights reserved.
ISP1362
EP0OUT
RESET
122 of 152
EP7
24
16
R
R
R
R
R
8
0
0
0
0
8
0
0
0
-
-

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