IDT821034DN IDT, Integrated Device Technology Inc, IDT821034DN Datasheet - Page 6

• Manufacturer Part Number: IDT821034DN
• Description: IC PCM CODEC QUAD MPI 52-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PCM Codec/Filterr

Specifications of IDT821034DN

• Data Interface: PCM Audio Interface
• Number Of Adcs / Dacs: 4 / 4
• Sigma Delta: No
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 52-MQFP, 52-PQFP
• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.75V
• Single Supply Voltage (max): 5.25V
• Package Type: PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 821034DN

corresponding 8-bit Gain Adjustment Registers: MSB GA Register,
which stores the 7 Most Significant bits of gain adjustment coefficient;
and LSB GA Register, which stores the 7 Least Significant bits of
gain adjustment coefficient. All Gain Adjustment Registers start with
‘0’. Gain Adjustment Registers can be accessed by specifying the
channel address (CR.3 and CR.2) in Configuration Register. If
CR[6:4] = ‘100’, CR.0 = ‘1’ and the leading data bit on CI pin is ‘0’ in
a microprocessor write cycle, the 8-bit data on CI pin is latched into
the selected MSB GA Register with MSB first; If CR[6:4] = ‘100’,
CR.0 = ‘0’ and the leading data bit on CI pin is ‘0’ in a microprocessor
write cycle, the 8-bit data on CI pin is latched into the selected LSB
GA Register with MSB first.
typical applications, the microprocessor will write control registers as ordered
pairs for CODEC Mode programming (Figure 2), SLIC Mode
programming (Figure 3), or Gain Mode programming (Figure 4). The
first write in the pair is to Configuration Register. This is identified by a
leading ‘1’ on CI pin. If CR.6 = ‘0’ after writing Configuration Register, the
programming is for CODEC mode and the succeeding operation is a
write cycle with a leading ‘0’ on CI pin. The write is intended for the
selected Time Slot Register. The timing diagram for CODEC Mode
programming is shown in Figure 11. If CR.6 = ‘1’ and CR.5 = ‘0’ and
CR.4 = ‘1’ after writing Configuration Register, the programming is for
SLIC control function and the succeeding operation is a read/write cycle.
The write, also with a leading ‘0’ on CI pin, is intended for the selected
SLIC Control Register, while the simultaneous read is from the SLIC
Status Register of the same channel. The timing diagram for SLIC Mode
programming is shown in Figure 10. If CR.6 = ‘1’, CR.5 = ‘0’ and CR.4
= ‘0’ after writing Configuration Register, the programming is for Gain
adjustment function and the succeeding operation is a write cycle with a
leading ‘0’ on CI pin. The write is intended for the selected Gain
Adjustment Register. The timing diagram for Gain Mode programming
is shown in Figure 13.
Gain Adjustment Registers are write only registers while SLIC Status
Registers are read only registers. Refer to Figure 12 for the detail timing
of the Serial Control Interface.
designed for IDT821034. This procedure is initiated when a ‘1111-1110’
command appears on CI. To read from the SLIC Status Registers when
using this method, Configuration Register should be set to indicate the
following operation is a SLIC programming, and then assert a ‘1111-1111’
command on CI. The data from SLIC Status Registers will clock out of CO
pin on CCLK rising edges when CS is low. The timing diagram of this method
is shown in Figure 14. When using this method, CO and CI pins can be
connected together. Either CO or CI will be in high Z state, depending on
the Serial Control Interface is in write cycle or read cycle. When a command
of ‘1111-1101’ appears on CI, the device will terminate this procedure.
IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN
All microprocessor cycles are either write cycles or read cycles. In
Configuration Register, Time Slot Registers, SLIC Control Registers and
An alternative method of receiving data from SLIC Status Register is
6
Figure 2. Registers for CODEC Mode Programming
Figure 3. Registers for SLIC Mode Programming
Figure 4. Registers for Gain Mode Programming
Configuration
SLIC Control
Configuration
Configuration
SLIC Status
Adjustment
Time Slot
Register
Register
Register
Register
Register
Register
Register
Figure 1. Serial Control Interface Signals
Gain
CCLK
Register
Indicator
Indicator
Register
Indicator
Register
Indicator
Register
Indicator
Register
Register
Indicator
CO
CS
CI
b7
'1'
'0'
'1'
'0'
'1'
'0'
CODEC
Mode
b6
b6
b6
'1'
'0'
b6
'1'
INDUSTRIAL TEMPERATURE RANGE
Image Data
Reserved
A/ -Law
Select
Mode
SLIC
Mode
b5
b5
Gain
b5
b5
'0'
b5
'0'
7 bits of Gain Adjustment
Timing
Mode
b4
b4
Coefficient
Interface
'1'
b4
b4
b4
'0'
Control
Serial
Time Slot
b3
b3
b3
b3
b3
b3
b3
Channel
Address
Channel
Address Transmit/
Channel
Address
Output Data
b2
b2
'0'
b2
b2
b2
b2
I/O Configuration
Transmit/Receive
Receive
b1
b1
b1
b1
'0'
b1
b1
Select
MSB/LSB
b0
b0
'0'
b0
b0
b0
b0