CS42325-CQZ Cirrus Logic Inc, CS42325-CQZ Datasheet - Page 64

• Manufacturer Part Number: CS42325-CQZ
• Description: IC CODEC STEREO AUDIO 48-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42325-CQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 95 / 100
• Voltage - Supply, Analog: 3.13 V ~ 3.47 V
• Voltage - Supply, Digital: 3.13 V ~ 3.47 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 2
• Conversion Rate: 96 KSPS
• Interface Type: Serial (I2C, SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 1 ADC/2 DAC
• Supply Current: 10 mA to 24 mA
• Thd Plus Noise: - 88 dB ADC / - 90 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

CS42325
7. GROUNDING AND POWER SUPPLY DECOUPLING
As with any high-resolution converter, the CS42325 requires careful attention to power supply and grounding ar-
rangements if its potential performance is to be realized.
Figure 7 on page 26
shows the recommended power ar-
rangements, with VA connected to a clean supply. VD, which powers the digital filter, may be run from the system
logic supply (VL) or may be powered from the analog supply (VA) via a resistor. In this case, no additional devices
should be powered from VD.
Power supply decoupling capacitors should be as near to the CS42325 as possible, with the low value ceramic ca-
pacitor being the nearest. All signals, especially clocks, should be kept away from the FILT+, VCM_ADC, VBIAS,
VCMBUF, and VCMDAC pins in order to avoid unwanted coupling into the modulators. The FILT+, VCM_ADC,
VBIAS, VCMBUF, and VCMDAC decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the
electrical path from each pin to GND. The CS42325 evaluation board demonstrates the optimum layout and power
supply arrangements. To minimize digital noise, connect the CS42325 digital outputs only to CMOS inputs.
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