CS42325-CQZ Cirrus Logic Inc, CS42325-CQZ Datasheet - Page 49

• Manufacturer Part Number: CS42325-CQZ
• Description: IC CODEC STEREO AUDIO 48-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42325-CQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 95 / 100
• Voltage - Supply, Analog: 3.13 V ~ 3.47 V
• Voltage - Supply, Digital: 3.13 V ~ 3.47 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 2
• Conversion Rate: 96 KSPS
• Interface Type: Serial (I2C, SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 1 ADC/2 DAC
• Supply Current: 10 mA to 24 mA
• Thd Plus Noise: - 88 dB ADC / - 90 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

DS838A2
6.3.6
6.4
6.4.1
6.4.2
6.4.3
6.4.4
SP1_M/S
7
Serial Port 1 Control (Address 03h)
Tri-State Serial Port 2
When enabled, and the device is configured as a master, then SCLK2 and LRCK2 of Serial Port 2 (SP2)
will be placed in a high-impedance output state. If Serial Port 2 is configured as a slave, SCLK2 and
LRCK2 will remain as inputs. SDIN1 and SDIN2 are always configured as inputs.
Serial Port 1 Master/Slave Select
This bit configures Serial Port 1 to operate as either a clock master or clock slave.
Serial Port 1 Speed Mode
In Master Mode this bit configures the speed mode of Serial Port 1.
MCLK1 Divider
These bits configure the internal MCLK1 dividers.
Serial Port 1 MCLK source
This bit selects which MCLK pin provides the clock for deriving Master Mode sub-clocks for Serial Port 1.
00
01
10
11
0
1
0
1
0
1
0
1
SP1_SPEED
SP1_MCLK
FREQ[1:0]
SP1_M/S
TRI-SP2
MCLK1
Reserved
6
÷1
÷1.5
÷2
÷3
SCLK2 and LRCK2 operate as inputs if Serial Port 2 is configured as a slave; SCLK2 and LRCK2
operate as outputs if Serial Port 2 is configured as a master
SCLK2 and LRCK2 operate as inputs if Serial Port 2 is configured as a slave; SCLK2 and LRCK2
become high-impedance outputs if Serial Port 2 is configured as a master
Slave Mode
Master Mode
Single-Speed Mode (SSM)
Double-Speed Mode (DSM)
MCLK1
MCLK2
Reserved
5
SP1_SPEED
4
Serial Port 1 Master/Slave Select
Serial Port 1 MCLK source
Serial Port 1 Speed Mode
SCLK2 and LRCK2 State
MCLK1
FREQ1
MCLK Divider
3
MCLK1
FREQ0
2
Reserved
1
CS42325
SP1_MCLK
0
49