CS42325-CQZ Cirrus Logic Inc, CS42325-CQZ Datasheet - Page 38

• Manufacturer Part Number: CS42325-CQZ
• Description: IC CODEC STEREO AUDIO 48-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42325-CQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 95 / 100
• Voltage - Supply, Analog: 3.13 V ~ 3.47 V
• Voltage - Supply, Digital: 3.13 V ~ 3.47 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 2
• Conversion Rate: 96 KSPS
• Interface Type: Serial (I2C, SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 1 ADC/2 DAC
• Supply Current: 10 mA to 24 mA
• Thd Plus Noise: - 88 dB ADC / - 90 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

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4.5.3
To minimize audible pops when turning off or placing the CODEC in standby:
4.5.2.1
1. Hold RST low until MCLK1 and the power supplies are stable.
2. Bring RST high (SDOUT must be pulled high).
3. Apply all LRCKx, SCLKx and SDIN signals for normal operation to begin.
4. Bring RST low if the analog or digital supplies drop below the recommended operating condition to
4.5.2.2
To minimize audible pops when turning off or placing the CODEC in standby:
1. Mute the SDIN1 and SDIN2 streams feeding the CODEC.
2. Bring RST low.
Software Mode Start-Up
When no pull-up on SDOUT is present, the Software Mode is accessible once RST is high. The desired
register settings can be loaded per the interface descriptions in
page
on page 47
VCMBUF, and the internal voltage references, FILT+ and VCM_ADC, will then begin powering up to nor-
mal operation. During this voltage reference ramp delay, both SDOUT and the AOUTxA/AOUTxB outputs
will be automatically muted. Once LRCKx is valid, MCLKx occurrences are counted over one LRCKx pe-
riod to determine the MCLKx/LRCKx frequency ratio and normal operation begins.
It is recommended that RST be activated if the analog or digital supplies drop below the recommended
operating condition to prevent power-glitch-related issues.
4.5.3.1
1. Hold RST low until the power supplies are stable.
2. Bring RST high, the device will be in “standby”.
3. Load the desired register settings while keeping the PDN bit set to ‘1’b.
4. Start MCLK1 (and MCLK2 if it is used) to the appropriate frequency, as discussed in
5. Set the PDN bit to ‘0’b.
6. Apply all LRCKx, SCLKx and SDIN signals for normal operation to begin.
7. Bring RST low if the analog or digital supplies drop below the recommended operating condition to
4.5.3.2
1. Using the appropriate registers, Mute the AOUTxA, AOUTxB, DAC’s & ADC’s.
2. Set the PDN bit in the power control register to ‘1’b. The CODEC will not power down until it reaches
3. Bring RST low.
prevent power glitch related issues.
prevent power glitch related issues.
a fully muted sate.
41. When the desired configuration is complete the PDN bit in
Recommended Power-Up Sequence, Hardware Mode
Recommended Power-Down Sequence, Hardware Mode
Recommended Power-Up Sequence, Software Mode
Recommended Power-Down Sequence, Software Mode
should be set to 0 to initiate the power up sequence. The quiescent voltage, VCMADC and
“Software Mode - I²C Control Port” on
“Operational Control (Address 02h)”
Section
CS42325
DS838A2
4.1.1.